calculate crc in vhdl 
Author Message
 calculate crc in vhdl

Hi all,

I need to calculate and verify a CRC in frames,  at more than  4 Gbps in a
FPGA.
The common CRC implementation is based on a linear feedback shift register
architecture which can be used to process 1 bit per clock cycle.
Easy but slow tyically only for low rates.

To meet the requirements of CRC calculation for gigabit networks, a solution
is
to calculate CRC32 in several steps using "Galois Method".. .

So I'm looking for a free VHDL Source code using this method in FPGA.
Can you help me please ?.

Thanx,
    Benoit.



Tue, 06 Sep 2005 16:40:17 GMT  
 calculate crc in vhdl

Quote:
> To meet the requirements of CRC calculation for gigabit networks, a
> solution is
> to calculate CRC32 in several steps using "Galois Method".. .

Can't you just recalculate the CRC32 to a 32 bits version (still too fast
for an FPGA?)? I've done similar things with scramblers and PRBS generators
(upto 256 bits:), so I would assume it can be done for a CRC32 just as
easily.

Regards,

Pieter Hulshoff



Tue, 06 Sep 2005 17:09:00 GMT  
 calculate crc in vhdl
On Fri, 21 Mar 2003 09:40:17 +0100, "Benoit"

Quote:

>Hi all,

>I need to calculate and verify a CRC in frames,  at more than  4 Gbps in a
>FPGA.
>The common CRC implementation is based on a linear feedback shift register
>architecture which can be used to process 1 bit per clock cycle.
>Easy but slow tyically only for low rates.

>To meet the requirements of CRC calculation for gigabit networks, a solution
>is
>to calculate CRC32 in several steps using "Galois Method".. .

>So I'm looking for a free VHDL Source code using this method in FPGA.
>Can you help me please ?.

I you had used a search engine, you would have found this code
generator:
http://www.easics.com/webtools/crctool

This produces VHDL for a parallel CRC generator.  You can also do it
using behavioural VHDL, such as this code by Mike Treseler
http://groups.google.com/groups?selm=3D937C88.2080602%40flukenetworks...

The later posts in this thread explain how parallel CRCs work and how
they can be pipelined for more speed:
http://groups.google.com/groups?threadm=c2088d4a.0111290138.10577818%...

But you also have to deal with the "ragged start word" or "ragged end
word" problems if you have a bus wider than 8 bits.  The issue is
discussed in this thread:
http://groups.google.com/groups?threadm=434d10fb.0302160949.75d1736f%...

Common bugs include bit ordering issues.  These can be quite
interesting to track down.
http://groups.google.com/groups?threadm=3E520A9C.9080206%40alcatel.no

Regards,
Allan.



Tue, 06 Sep 2005 17:15:37 GMT  
 
 [ 3 post ] 

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