DLL of a Virtex FPGA and FPGA Express V3.3 
Author Message
 DLL of a Virtex FPGA and FPGA Express V3.3

Hi boys,

I have some problems with the DLL of a Virtex FPGA and FPGA Express
V3.3.
If I use the DLL, the FPGA Express show me that warning:

Warning: Port 'rclk_i' has no net attached to it - no pad cells inserted
at this port.  (FPGA-PADMAP-2)

-->  the timing simulation fails.

If I dont use the DLL, that warning dont appear, and the simulation
runs good.
How can I force the FPGA Express to use the IBUFG for that signal, if I
use the DLL?

Thank you

Helga



Mon, 17 Feb 2003 21:01:16 GMT  
 DLL of a Virtex FPGA and FPGA Express V3.3
Hi.

Can I suggest posting the appropriate part of you VHDL code, and maybe we
can see what the problem is.

I've used DLLs with Virtex & FPGA Epress, and had no problems simulating.

Quote:
>Warning: Port 'rclk_i' has no net attached to it - no pad cells inserted
>at this port.  (FPGA-PADMAP-2)

Usually, you con'd have to be worried about this ... You have told FPGA
Express to automatically insert I/O buffers on all the signls in the 'port'
definition of your entity'.  It is just warning you that since you've hand-
instantiated a buffer for this pin, it hasn't done one automatically.

Quote:
>-->  the timing simulation fails.

Are you 100% sure that it fails?
I found what I did the same thing that in the simulation, the DLL took a
long time to lock onto the input signal, and that there was no clock output
until it did.
So perhaps in your simulation, you're applying stimulus, and expecting
results, before the DLL has locked onto the input signal.

Ty letting your simulation run for a long time, and see if after that long
time, if you odn't have a clock output.

Hope this helps.

-Kent



Tue, 18 Feb 2003 08:34:08 GMT  
 DLL of a Virtex FPGA and FPGA Express V3.3
You are right,
it was a problem in my design.

Thanks
Helga

"K. Orthner" schrieb:

Quote:
> Hi.

> Can I suggest posting the appropriate part of you VHDL code, and maybe we
> can see what the problem is.

> I've used DLLs with Virtex & FPGA Epress, and had no problems simulating.

> >Warning: Port 'rclk_i' has no net attached to it - no pad cells inserted
> >at this port.  (FPGA-PADMAP-2)

> Usually, you con'd have to be worried about this ... You have told FPGA
> Express to automatically insert I/O buffers on all the signls in the 'port'
> definition of your entity'.  It is just warning you that since you've hand-
> instantiated a buffer for this pin, it hasn't done one automatically.

> >-->  the timing simulation fails.

> Are you 100% sure that it fails?
> I found what I did the same thing that in the simulation, the DLL took a
> long time to lock onto the input signal, and that there was no clock output
> until it did.
> So perhaps in your simulation, you're applying stimulus, and expecting
> results, before the DLL has locked onto the input signal.

> Ty letting your simulation run for a long time, and see if after that long
> time, if you odn't have a clock output.

> Hope this helps.

> -Kent



Tue, 18 Feb 2003 22:34:47 GMT  
 
 [ 3 post ] 

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