Precedence and associativity - ill-defined in IEEE std? 
Author Message
 Precedence and associativity - ill-defined in IEEE std?

Hello comp.lang.vhdl.all,

When compiling the following test-code I encounter syntax errors, both in my
simulator and synthesis tool. This leads me to conclude that it involves a
language feature. The type involved (std_logic, bit, boolean) makes no
difference.

--      Error:
--      a<=b and c or d;

--      OK:
--      a<=(b and c )or d;

--      OK:
--      a<=b and (c or d);

Section 7.2 of the 1993 LRM defines the precedence of "and" and "or" as being
equal. The subsequent paragraph (p.92 line 55) specifies equal-precedence
operators must be evaluated in textual (left-to-right) order. However, the
sentence describing this textual order is qualified by the condition "Where
the language allows a sequence of operators". I don't find any obvious
definition of where such a sequence is allowed. The only paragraph coming
close can be found just before 7.2 (p.92 line 40) where I read:

NOTE- The syntax for an expression involving logical operators allows a
sequence of and, or, xor or xnor operators since the corresponding predefined
operators are associative.

I agree that not allowing operators with equal precedence to be intermixed
(esp. since "and" usually has greater precedence than "or" in Boolean algebra
notations) is a Good Thing. I just wanted to know:

* Is the aforementioned NOTE the cause of my error messages, or is there
another -perhaps clearer- clause tucked away somewhere in the LRM ?
* If the previous answer is "yes", isn't the sentence "sequence of and, or, or
xnor operators" ambiguous since it does not mention whether it involves a
sequence of the same operator or any of the operators mentioned?

I hope any of the language lawyers (Paul?) can elaborate on this.

Thanks in advance,

Hendrik De Vloed --  A4000/40 -- Aminet:hard/hack/lcdaemon.lha
-- Barco Silex FPGA/ASIC design   --   http://www.*-*-*.com/ --
***   #include<these_are_my_opinions_legal_mumbo_jumbo.h>  ***
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Sat, 30 Dec 2000 03:00:00 GMT  
 Precedence and associativity - ill-defined in IEEE std?

: When compiling the following test-code I encounter syntax errors, both in my
: simulator and synthesis tool. This leads me to conclude that it involves a
: language feature. The type involved (std_logic, bit, boolean) makes no
: difference.

: --      Error:
: --      a<=b and c or d;

: --      OK:
: --      a<=(b and c )or d;

: --      OK:
: --      a<=b and (c or d);

: Section 7.2 of the 1993 LRM defines the precedence of "and" and "or" as being
: equal. The subsequent paragraph (p.92 line 55) specifies equal-precedence
: operators must be evaluated in textual (left-to-right) order. However, the
: sentence describing this textual order is qualified by the condition "Where
: the language allows a sequence of operators". I don't find any obvious
: definition of where such a sequence is allowed. The only paragraph coming
: close can be found just before 7.2 (p.92 line 40) where I read:

: NOTE- The syntax for an expression involving logical operators allows a
: sequence of and, or, xor or xnor operators since the corresponding predefined
: operators are associative.

: I agree that not allowing operators with equal precedence to be intermixed
: (esp. since "and" usually has greater precedence than "or" in Boolean algebra
: notations) is a Good Thing. I just wanted to know:

: * Is the aforementioned NOTE the cause of my error messages, or is there
: another -perhaps clearer- clause tucked away somewhere in the LRM ?

If you carefully follow the EBNF in section 7.1, you will see that you
cannot freely intermix operators without the use of parentheses.
I.e., the BNF is *not*:

        expression ::= relation { logical_operator relation }

Instead, it is

        expression ::=
                  relation { _and_  relation }
                | relation { _or_   relation }
                | relation { _xor_  relation }
                | relation [ _nand_ relation ]
                | relation [ _not_  relation ]
                | relation { _xnor_ relation }

Notice that curly-braces are used around the associative operators,
thus allowing A and B and C.  However, square brackets are used around
non-associative operators, thus disallowing A nand B nand C.

The reason for all this?  Simple, (A and B) or C /= A and (B or C) and
(A nand B) nand C /= A nand (B nand C), and one of VHDL's guiding principles
is to prevent silly mistakes.

: * If the previous answer is "yes", isn't the sentence "sequence of and, or, or
: xnor operators" ambiguous since it does not mention whether it involves a
: sequence of the same operator or any of the operators mentioned?

No, it's not ambiguous, it's illegal.

Hope this helps,

Paul

--

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Sat, 30 Dec 2000 03:00:00 GMT  
 
 [ 2 post ] 

 Relevant Pages 

1. OCaml operator precedence and associativity

2. IEEE Standard Subroutines for CAMAC (ANSI/IEEE Std 758-1979)

3. Std:Cut, Std:Copy, Std:Paste - Don't work at all

4. Std:Copy, Std:Paste, Std:cut problems

5. precedence of defined operations (in f07?)

6. defined op precedence in f2007?

7. begin vs lambda in ieee std

8. worse is worse (how to win, at last)

9. $monitor and IEEE Std 1364

10. IEEE Std 1076.3-1996

11. IEEE std. VHDL compiler

12. IEEE Std. 754-1985

 

 
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