need help in xilinx student edition 2i 
Author Message
 need help in xilinx student edition 2i

Hi,
1. Is there any example to create a testbench *.vhd and simulate it
using xilinx student edition 2i (XSE 2i). I tried some example with
testbench .vhd but everytime I compiled there will be an error '***(eg
wait) statement is not supported for synthesis'

2.  How to use XS40 test board and user constrained file (.ucf)  to
test for a lot of input. For example

ENTITY uart IS
  PORT(
    hclk   : IN     std_logic;   -- host clock
    reseth : IN     std_logic;   -- async reset
    cs     : IN     std_logic;   -- chip select
    rw     : IN     std_logic;   -- read/write
    addr   : IN     std_logic_vector(2 DOWNTO 0);-- host address
    data   : INOUT  std_logic_vector(7 DOWNTO 0);-- host data
    ack    : OUT    std_logic;   -- transfer acknowledge to host
    irq    : OUT    std_logic;   -- interrupt request to host
    cts    : IN     std_logic;   -- clear to send
    rts    : OUT    std_logic;   -- ready to send
    rxd    : IN     std_logic;   -- received serial data
    txd    : OUT    std_logic    -- transmitted serial data
        );
END ENTITY uart;

Is there any example?

Thanks....



Mon, 16 Feb 2004 12:36:50 GMT  
 need help in xilinx student edition 2i
1) If you want to simulate your design you need a
   VHDL simulator. Xilinx Student edition is a
   synthesis tool that maps your design on a
   xilinx component. And synthesis tools support
   a subset of VHDL, e.g. not WAIT FOR statements,
   explicit delays, access types, ... etc. etc.

2) I think you are using a board of XESS.
   Beneath a simple design I made with this board.
   File dice1.vhd: contains the design
   File dice1.ucf: constraint (in this case pin location only)
   Then you need the tooling (XSLOAD) you received with you
   XS-board (or go to www.xess.com):
   and type:
     xsload xilrout.bit
   (xilrout.bit is the generated bit file with foundation
    for you design). When I'm remember you also need
    a file D4005xlp.bit that came with your XESS tooling.)

I hope this helps

Egbert Molenkamp

FILE: DICE.VHD
-- asynchrone inputs !!!
-- 7-segment display
--
--     +--6--+
--     |     |
--     5     4
--     |     |
--     +--3--+
--     |     |
--     2     1
--     |     |
--     +--0--+

ENTITY dice1 IS
  PORT (clk     : IN bit;
        reset   : IN bit;
        button  : IN bit;
        display : OUT bit_vector(0 TO 6));
END dice1;

ARCHITECTURE behavior OF dice1 IS
BEGIN

  PROCESS
    VARIABLE diceval : INTEGER RANGE 1 TO 6;
  BEGIN
    WAIT UNTIL clk='1';
    IF reset='0'
      THEN diceval := 1;
      ELSIF diceval >= 6
        THEN diceval := 1;
        ELSE diceval := diceval + 1;
    END IF;
    IF button='0' OR reset='0' THEN
      CASE diceval IS     --  0123456
        WHEN 1 => display <= "0100100";
        WHEN 2 => display <= "1011101";
        WHEN 3 => display <= "1101101";
        WHEN 4 => display <= "0101110";
        WHEN 5 => display <= "1101011";
        WHEN 6 => display <= "1111011";
      END CASE;      
    END IF;
  END PROCESS;
END behavior;

FILE DICE.UCF
net clk         loc=p13;
net display<0>  loc=p25;
net display<1>  loc=p26;
net display<2>  loc=p24;
net display<3>  loc=p20;
net display<4>  loc=p23;
net display<5>  loc=p18;
net display<6>  loc=p19;
net reset       loc=p3;
net button      loc=p4;

Quote:

> Hi,
> 1. Is there any example to create a testbench *.vhd and simulate it
> using xilinx student edition 2i (XSE 2i). I tried some example with
> testbench .vhd but everytime I compiled there will be an error '***(eg
> wait) statement is not supported for synthesis'

> 2.  How to use XS40 test board and user constrained file (.ucf)  to
> test for a lot of input. For example

> ENTITY uart IS
>   PORT(
>     hclk   : IN     std_logic;   -- host clock
>     reseth : IN     std_logic;   -- async reset
>     cs     : IN     std_logic;   -- chip select
>     rw     : IN     std_logic;   -- read/write
>     addr   : IN     std_logic_vector(2 DOWNTO 0);-- host address
>     data   : INOUT  std_logic_vector(7 DOWNTO 0);-- host data
>     ack    : OUT    std_logic;   -- transfer acknowledge to host
>     irq    : OUT    std_logic;   -- interrupt request to host
>     cts    : IN     std_logic;   -- clear to send
>     rts    : OUT    std_logic;   -- ready to send
>     rxd    : IN     std_logic;   -- received serial data
>     txd    : OUT    std_logic    -- transmitted serial data
>         );
> END ENTITY uart;

> Is there any example?

> Thanks....



Mon, 16 Feb 2004 15:43:10 GMT  
 
 [ 2 post ] 

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