Use of VHDL Records in ASIC Design Flow ? 
Author Message
 Use of VHDL Records in ASIC Design Flow ?

Hi,

I am working on the design of a big ASIC that performs complex data
manipulation in VHDL.  I would like to know if it is safe to use VHDL
array of records (containing a mix of std_logic and std_logic_vectors)
to pass data between modules.  It is my intent to use them in the lower
levels of the hierarchy. The main reason is that is simplifies the
module interfaces, makes the code easier to understand and keeps related
information together.

I also respect the VHDL Synthesis subset, and so far, I am able to
synthesize with Synopsys and Exemplar Leonardo.

I am worried that at some point in the flow I might get problems.  These
problems could come from the need to generate the final netlist in
Verilog which I was told does not support arrays of vectors, nor
records.

The ASICs vendor might be Toshiba, NEC or Lucent.  We use Synopsys
Design Compiler and we want to use Formality for some of the
verifications.  The technology would likely be 0.18 or 0.14 microns
(which I am guessing would mean tools that are rather up to date ?).  We
also intend to keep the hierarchy in the design for potential last
minute ECO's.

Has any of you designed using records and encountered problems with
synthesis or vendor backend tools ? I would appreciate if you could
share your experience or thoughts on the matter.

Thank you very much for your time,

J-Samuel



Wed, 22 Jan 2003 03:00:00 GMT  
 Use of VHDL Records in ASIC Design Flow ?
If you can pass the code through the synthesis tools, this is good, but you
also need to verify if your
simulation tool will also digest the code.   I've found that sometimes
tricky code that synthesizes will
not simulate.    It's not what you expect, but it happens..  As regards the
Verilog output, it will certainly
be a verilog netlist (structural Verilog), and the element names will be
expanded by that point.   You
won't be able to convert back to the original VHDL records, but you should
be able to figure out the
original source point for the array names.

John McCluskey

Quote:

> Hi,

> I am working on the design of a big ASIC that performs complex data
> manipulation in VHDL.  I would like to know if it is safe to use VHDL
> array of records (containing a mix of std_logic and std_logic_vectors)
> to pass data between modules.  It is my intent to use them in the lower
> levels of the hierarchy. The main reason is that is simplifies the
> module interfaces, makes the code easier to understand and keeps related
> information together.

> I also respect the VHDL Synthesis subset, and so far, I am able to
> synthesize with Synopsys and Exemplar Leonardo.

> I am worried that at some point in the flow I might get problems.  These
> problems could come from the need to generate the final netlist in
> Verilog which I was told does not support arrays of vectors, nor
> records.

> The ASICs vendor might be Toshiba, NEC or Lucent.  We use Synopsys
> Design Compiler and we want to use Formality for some of the
> verifications.  The technology would likely be 0.18 or 0.14 microns
> (which I am guessing would mean tools that are rather up to date ?).  We
> also intend to keep the hierarchy in the design for potential last
> minute ECO's.

> Has any of you designed using records and encountered problems with
> synthesis or vendor backend tools ? I would appreciate if you could
> share your experience or thoughts on the matter.

> Thank you very much for your time,

> J-Samuel



Wed, 22 Jan 2003 03:00:00 GMT  
 Use of VHDL Records in ASIC Design Flow ?
I've worked on a design for ASIC using arrays of records and records on the
port maps (though never arrays on the port maps).  There are some issues
with backend tools but nothing too difficult to overcome.  I found
simulation easier using records (added more structure to waves).  You need
to be careful with coding styles though - it's a good idea to test exactly
what you can use before you begin.  It's a lot of work later on to find that
synopsys doesn't like aggregate record element assignments in resets (or
anywhere for that matter).

Quote:

> > Hi,

> > I am working on the design of a big ASIC that performs complex data
> > manipulation in VHDL.  I would like to know if it is safe to use VHDL
> > array of records (containing a mix of std_logic and std_logic_vectors)
> > to pass data between modules.  It is my intent to use them in the lower
> > levels of the hierarchy. The main reason is that is simplifies the
> > module interfaces, makes the code easier to understand and keeps related
> > information together.

> > ...

> > Has any of you designed using records and encountered problems with
> > synthesis or vendor backend tools ? I would appreciate if you could
> > share your experience or thoughts on the matter.

> > Thank you very much for your time,

> > J-Samuel

A.


Fri, 24 Jan 2003 03:00:00 GMT  
 Use of VHDL Records in ASIC Design Flow ?

I was curious while reading your post ...

Quote:
>The ASICs vendor might be Toshiba, NEC or Lucent.  We use Synopsys
>Design Compiler and we want to use Formality for some of the
>verifications.  The technology would likely be 0.18 or 0.14 microns
>(which I am guessing would mean tools that are rather up to date ?).  We
>also intend to keep the hierarchy in the design for potential last
>minute ECO's.

I've been doing ASIC for awhile and we have always wanted to do keep
hierarchy after going through our layout flow. I've gone through 3 different
flows and none of them have been able to preserve hierarchy after layout,
i.e. we always end up with a flat gate-level netlist which is a problem
because front-end tools don't support big flat designs. I'm just curious to
know what tools you use that preserve the hierarchy after going through
layout.

Regards,

Koutou



Fri, 24 Jan 2003 03:00:00 GMT  
 Use of VHDL Records in ASIC Design Flow ?

Quote:

>Has any of you designed using records and encountered problems with
>synthesis or vendor backend tools ? I would appreciate if you could
>share your experience or thoughts on the matter.

A good example of a complex IP core using records is ESA's LEON SPARC V8 Core
(you can download the code from http://www.estec.esa.nl/wsmwww/leon/). For FPGA's
only Synplicity can handle it (Synthesis takes just 15 minutes!)

Hans.

Quote:

>Thank you very much for your time,

>J-Samuel



Sat, 25 Jan 2003 03:00:00 GMT  
 Use of VHDL Records in ASIC Design Flow ?
Most of the backend tools are preserving the hierarchy in the instance names,
even if the layout is a flatten one.

Try to make a Verilog netlist from a Silicon Ensemble layout, you will
see that the hierarchy is preserved.

Regards,

Kholdoun TORKI

http://cmp.imag.fr

Quote:

> I was curious while reading your post ...

> >The ASICs vendor might be Toshiba, NEC or Lucent.  We use Synopsys
> >Design Compiler and we want to use Formality for some of the
> >verifications.  The technology would likely be 0.18 or 0.14 microns
> >(which I am guessing would mean tools that are rather up to date ?).  We
> >also intend to keep the hierarchy in the design for potential last
> >minute ECO's.

> I've been doing ASIC for awhile and we have always wanted to do keep
> hierarchy after going through our layout flow. I've gone through 3 different
> flows and none of them have been able to preserve hierarchy after layout,
> i.e. we always end up with a flat gate-level netlist which is a problem
> because front-end tools don't support big flat designs. I'm just curious to
> know what tools you use that preserve the hierarchy after going through
> layout.

> Regards,

> Koutou



Sat, 01 Feb 2003 03:00:00 GMT  
 
 [ 6 post ] 

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