simulating a Dual Ported RAM 
Author Message
 simulating a Dual Ported RAM

Hi,

when I simulate the Dual Port RAM described below, the simulator stops
with the message "potential zero loop detected" in the process
MEM_ACCESS.
First I only used one process but the error was the same.
The simulation runs ok for some time and I can access the RAM,
but then without accessing the RAM it prompts this error.

I use the Summit tools (Visual HDL) for design entry and simulation.

Can anyone help me to find the cause of this problem?

thanks

        Gerd Dietrich

--------------------------------------------------------------------
architecture  RTL  of  IDT_70V25  is

    type DPR_8 is array (0 to 256) of std_logic_vector (7 downto 0);
    signal MEM_HI : DPR_8;
    signal MEM_LO : DPR_8;
    signal WR_L : std_logic ; -- write left
    signal WR_R : std_logic ; -- write right
    signal RD_L : std_logic ; -- read left
    signal RD_R : std_logic ; -- read right

begin

    -- read and write signal for left and right port
    CTRL_SIGNALS : process (CE_L, RW_L, OE_L, CE_R, RW_R, OE_R)
    begin
        if (CE_L = '0' and RW_L = '0' and OE_L = '1') then
                WR_L <= '0';
                RD_L  <= '1';
        elsif (CE_L = '0' and RW_L = '1' and OE_L = '0') then
                WR_L <= '1';
                RD_L  <= '0';
        else -- no read, no write
                WR_L <= '1';
                RD_L  <= '1';
        end if ;
        if (CE_R = '0' and RW_R = '0' and OE_R = '1') then
                WR_R <= '0';
                RD_R  <= '1';
        elsif (CE_R = '0' and RW_R = '1' and OE_R = '0') then
                WR_R <= '1';
                RD_R  <= '0';
        else -- no read, no write
                WR_R <= '1';
                RD_R  <= '1';
        end if ;
    end process ; -- control signals

    MEM_ACCESS : process (WR_L, RD_L, LB_L, UB_L, ADR_L, IO_L,
                          WR_R, RD_R, LB_R, UB_R, ADR_R, IO_R)
        variable left_pt  : integer ;
        variable right_pt : integer ;
    begin
        -- access from left
        left_pt  := conv_integer (ADR_L (7 downto 0));
        right_pt := conv_integer (ADR_R (7 downto 0));
        if (WR_L'event and WR_L = '1') then -- rising edge of write left
                if (LB_L = '0') then -- write LOW
                        MEM_LO (left_pt) <= IO_L (7 downto 0);
                end if;
                if (UB_L = '0') then -- write HIGH
                        MEM_HI (left_pt) <= IO_L (15 downto 8);
                end if;
        elsif (RD_L = '0') then -- read left
                IO_L (7 downto 0)  <= MEM_LO (left_pt);
                IO_L (15 downto 8) <= MEM_HI (left_pt);
        else
                IO_L <= (others => 'Z');
        end if; -- access from left

        -- access from right
        if (WR_R'event and WR_R = '1') then -- rising edge of write right
                if (LB_R = '0') then -- write LOW
                        MEM_LO (right_pt) <= IO_R (7 downto 0);
                end if;
                if (UB_R = '0') then -- write HIGH
                        MEM_HI (right_pt) <= IO_R (15 downto 8);
                end if;
        elsif (RD_R = '0') then -- read right
                IO_R (7 downto 0)  <= MEM_LO (right_pt);
                IO_R (15 downto 8) <= MEM_HI (right_pt);
        else
                IO_R <= (others => 'Z');
        end if; -- access from left

    end process;
end;
--------------------------------------------------------------------------

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Sun, 19 May 2002 03:00:00 GMT  
 simulating a Dual Ported RAM

Quote:

> when I simulate the Dual Port RAM described below, the simulator stops
> with the message "potential zero loop detected" in the process
> MEM_ACCESS.
>     MEM_ACCESS : process (WR_L, RD_L, LB_L, UB_L, ADR_L, IO_L,
>                           WR_R, RD_R, LB_R, UB_R, ADR_R, IO_R)
....
>     begin
....
>                 IO_L (7 downto 0)  <= MEM_LO (left_pt);
>                 IO_L (15 downto 8) <= MEM_HI (left_pt);
>         else
>                 IO_L <= (others => 'Z');
>         end if; -- access from left

Here you are assigning to a signal (IO_L) that is in the sensitivity
list of the process.  This asignment will cause the process to get
re-evaluated ad infinitum.

Unfortunately you want it in the process as it is a bidirectional signal
that is read for writes.

There are various possible solutions.  One is to split it into two
processes, one for reading that is not sensitive to IO_L and another
that is sensitive to it for writing.

--Phil.



Sun, 19 May 2002 03:00:00 GMT  
 simulating a Dual Ported RAM
Hi,

I changed the VHDL now and I have to processes, but this did not help,
the process :

    MEM_READ : process (RD_L, ADR_L, RD_R, ADR_R)
    begin
        -- read from left
        if (RD_L = '0' and RD_R = '1') then
                IO_L (7 downto 0)  <= MEM_LO (conv_integer (ADR_L (7 downto 0)));
                IO_L (15 downto 8) <= MEM_HI (conv_integer (ADR_L (7 downto 0)));
                IO_R <= (others => 'Z');
        -- read from right
        elsif (RD_L = '1' and RD_R = '0') then
                IO_L <= (others => 'Z');
                IO_R (7 downto 0)  <= MEM_LO (conv_integer (ADR_R (7 downto 0)));
                IO_R (15 downto 8) <= MEM_HI (conv_integer (ADR_R (7 downto 0)));
        -- read from left and right
        elsif (RD_L = '0' and RD_R = '0') then
                IO_L (7 downto 0)  <= MEM_LO (conv_integer (ADR_L (7 downto 0)));
                IO_L (15 downto 8) <= MEM_HI (conv_integer (ADR_L (7 downto 0)));
                IO_R (7 downto 0)  <= MEM_LO (conv_integer (ADR_R (7 downto 0)));
                IO_R (15 downto 8) <= MEM_HI (conv_integer (ADR_R (7 downto 0)));
        -- no read at all
        else
                IO_L <= (others => 'Z');
                IO_R <= (others => 'Z');
        end if; -- access from left
    end process; -- memory read

still prompts the error "potential zero delay loop detected".
thanks for your help

        Gerd

Quote:


> > when I simulate the Dual Port RAM described below, the simulator stops
> > with the message "potential zero loop detected" in the process
> > MEM_ACCESS.

> >     MEM_ACCESS : process (WR_L, RD_L, LB_L, UB_L, ADR_L, IO_L,
> >                           WR_R, RD_R, LB_R, UB_R, ADR_R, IO_R)
> ....
> >     begin
> ....
> >                 IO_L (7 downto 0)  <= MEM_LO (left_pt);
> >                 IO_L (15 downto 8) <= MEM_HI (left_pt);
> >         else
> >                 IO_L <= (others => 'Z');
> >         end if; -- access from left

> Here you are assigning to a signal (IO_L) that is in the sensitivity
> list of the process.  This asignment will cause the process to get
> re-evaluated ad infinitum.

> Unfortunately you want it in the process as it is a bidirectional signal
> that is read for writes.

> There are various possible solutions.  One is to split it into two
> processes, one for reading that is not sensitive to IO_L and another
> that is sensitive to it for writing.

> --Phil.

--

Switching Test Solutions AG   |   http://www.stest.com
Friesenbergstr. 75            |   Phone: +41 1 454 65 37
CH - 8055 Zuerich             |   FAX:   +41 1 454 66 05


Sun, 19 May 2002 03:00:00 GMT  
 simulating a Dual Ported RAM
the last time i had an infinite loop in my code, i gone step by step
through the code and found the problem quite fast. i assume you should
do the same.

Kai
------------------------------------------
Dipl. Ing. Kai Troester

IMMS - Institut fuer Mikroelektronik-
und Mechatronik-Systeme gGmbH

Langewiesener Strasse 22
98693 Ilmenau
Germany
Tel:    +49(3677)6783-42
Fax:    +49(3677)6783-38

-------------------------------------------



Mon, 20 May 2002 03:00:00 GMT  
 
 [ 4 post ] 

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