VHDL Modeling Enhancement Initiative 
Author Message
 VHDL Modeling Enhancement Initiative

Dear Colleagues,

This is a general call for anyone who is
interested in the topic discussed below
and would like to work within the VASG
to define ways in which VHDL can be
enhanced within the scope of this topic.

At the Paris "Future of VHDL Workshop," I
presented on the topic of _RTL Modeling
Enhancements_.  I'm glad to report that
my presentation was well received at the
Paris Workshop.  The same presentation
was also well received by a small group of
users in the U.K. and by a group of VeriBest

To quickly summarize the presentation
and the proposed work topic for VASG:

Designers are frequently frustrated by
the lack of domain-specific features in
VHDL.  This short-coming in VHDL results
in designers spending more time than
potentially necessary to create and verify
designs due to the need to also model
these common electronic domain-specific
objects and models or work-around other
language deficiencies.  This initiative is
about making the designer's life easier
by providing these objects, models and
language features as part of VHDL.

The following list provides a flavor of the
types of things that this proposed VASG
committee would explore.  It is meant as a
starting point and, as such, suggestions are
welcome for other items to add to the list
for exploration.  (Note, view this as an
initial set of requirements; this is not
meant to imply any kind of language
design other than an easier way of doing
the following than exists with VHDL today.)

1.  Types and operations:
    a.  Better mapping between bit (std_logic)
         and integers.
    b.  Better mapping between bit (std_logic)
         and reals (potentially fixed point support).
    c.  Bit-wise operations on integers.
    d.  Richer operator support (unary-reduction
         modes, etc.)
    e.  Don't care value meaning in case statements.

2.  Predefined register and latch type objects.

3.  Predefined clock objects.

4.  Better language support for defining state
     machines (and perhaps truth tables).

5.  Expressions in static sensitivity lists
     (edge and combinatorial type expressions).

6.  PCB modeling enhancements: resistor and
     strap models.

7.  More I/O improvements.

If you are interested in actively contributing or
simply monitoring/commenting on work in this
area, please send me email

I am hoping to get the committee approved
by VASG and organized by the Fall VIUF
timeframe.  (Attendance at the VIUF is not required for

Stephen Bailey
Chairman, VHDL Analysis and Standardization Group (VASG)
VeriBest Inc.
6101 Lookout Rd., Suite A
Boulder, CO 80301

voice: 303-581-2467                fax: 303-581-9972

Fri, 14 Jan 2000 03:00:00 GMT  
 [ 1 post ] 

 Relevant Pages 

1. c model convert to verilog/VHDl model

2. FTP Site for VHDL models in THE VHDL HANDBOOK, by David Coelho

3. Recursive VHDL models - how to prang your VHDL tools

4. OO enhancements to VHDL

5. VHDL Enhancements ('DRIVER)

6. VHDL Enhancements

7. Object models, Domain models, Application models, and MVC?

8. Object models, Domain models, Application models, and MVC?

9. Looking for freely available SDRAM VHDL model

10. Memory Models for VHDL/Verilog

11. Vhdl/verilog model for flash memories

12. Verilog/VHDL models for VME


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