More signed/unsigned arithmetic craziness

Borrowing a little from the "other joe's" code:

library ieee;

use ieee.std_logic_1164.all;

use ieee.numeric_std.all;

entity test is end test;

architecture behave of test is

signal interp_o : signed(47 downto 0); --Size = Sum of Size of args

signal pa_i, pb_i : signed(23 downto 0);

signal interp_i : unsigned(15 downto 0);

begin

-- type casting signed( ...) can be used to convert

-- closely related types with common indices.

-- Hence, these can be used to convert between:

-- signed, unsigned, and std_logic_vector

-- For unsigned to signed, the '0' is added to ensure

-- the MSB = Left most indice = Sign Bit = 0

interp_o <= (pa_i + signed('0' & interp_i)) * (pb_i - pa_i);

end behave;

Cheers,

Jim

--

~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~

Jim Lewis

SynthWorks Design Inc. http://www.SynthWorks.com

1-503-590-4787

Expert VHDL Training for Hardware Design and Verification

~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~

Quote:

> Hello again.

> Well, I hope I'm slightly more informed this time. After

> working with an unsigned implementation of a linear interpolator, I

> realized I needed to use two's compliment arithmetic for the data. The

> problem with this is that one of the operands in the algorithm I'm

> implementing in VHDL is unsigned. I've also converted all of my code

> over to the numeric_std library, but I can't do something like:

> (pa_i + interp) * (pb_i - pa_i)

> when pa_i and pb_i are signed 24-bit values and interp is a 16-bit

> unsigned value. I've tried the following things to get around this

> with P1076.3:

> - using the TO_SIGNED function. Unfortunately, upon browsing the

> source code for the numeric_std package, there's only one

> implementation of this function which converts from integers to the

> signed format in numeric_std.

> - Direct assignment. I tried creating a 24-bit signed signal, then

> assigning a padded version of the 16-bit unsigned signal to the signed

> signal like so:

> signal interp_temp : signed(23 downto 0);

> ...

> interp_temp <= "00000000" & interp_i;

> Additionally, the version of numeric_std I have doesn't have an

> overloaded operator for adding signed and unsigned quantities (for

> good reason IMHO), so how do I do this?

> Regards,

> Joe

--

~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~

Jim Lewis

SynthWorks Design Inc. http://www.SynthWorks.com

1-503-590-4787

Expert VHDL Training for Hardware Design and Verification

~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~