Testing HW/SW Integration with Model Tech 
Author Message
 Testing HW/SW Integration with Model Tech



Quote:
>Has anyone tried to test hardware/software integration by developing a
>VHDL model of their hardware, and using MT to simulate the HW while
>the software is interacting with the simulation input/output from MT?
>I can see how to do a limited form of this in a batch mode, where the
>SW portion creates a stimulus set of vectors, the HW model reads in
>the  stimulus through textio, and writes the outputvalues thru textio
>as well., then the SW reads this output file. Of course, this seems
>pretty limited...has anyone developed a better approach? I understand
>there is a C interface with MT, but I'm not sure how to use it in this
>type of application.

Yes,
I did it; see another set of posts to comp.lang.vhdl (out a couple of days
ago) on this very topic.

There are several ways to do system sim with software:
- behavi{*filter*}C code that interacts with VHDL simulator
        (i.e. you application software is run, and whenever it accesses
        a hardware register, the C process is paused, the VHDL simulator
        is invoked, and then the value read from VHDL hardware register
        is returned to the C process).
        MTI can't do this; I've talked to them about it.
- C code, running as a subroutine to the VHDL simulator.
        MTI can do this.  You can model software things that are totally
        re-entrant, or you need to create registers to keep track of your
        execution point in your C code, if you wish to return to the same
        place you left off.  You can model CPUs in this way, by having
        a progam-counter, etc.

        MTI can do this; I have used a model from ARM to simulate hardware
        and software working together.

- C code and simulator interacting via data files
        This is problematical: how do you pause the entire VHDL simulator,
        while waiting for your C code to process the VHDL output, and present
        new input to the VHDL simulator?

The best/cleanest approach is to implement true inter-process communication
between the VHDL simulation process and the C process.  Vantage does this;
MTI doesn't (but MTI can work for some cases).

I did a paper on this, at PLD-con 1995.

Hope this helps,
Erik Jessen



Mon, 09 Mar 1998 03:00:00 GMT  
 Testing HW/SW Integration with Model Tech
Has anyone tried to test hardware/software integration by developing a
VHDL model of their hardware, and using MT to simulate the HW while
the software is interacting with the simulation input/output from MT?
I can see how to do a limited form of this in a batch mode, where the
SW portion creates a stimulus set of vectors, the HW model reads in
the  stimulus through textio, and writes the outputvalues thru textio
as well., then the SW reads this output file. Of course, this seems
pretty limited...has anyone developed a better approach? I understand
there is a C interface with MT, but I'm not sure how to use it in this
type of application.


Tue, 10 Mar 1998 03:00:00 GMT  
 Testing HW/SW Integration with Model Tech

Quote:



>>Has anyone tried to test hardware/software integration by developing a
>>VHDL model of their hardware, and using MT to simulate the HW while
>>the software is interacting with the simulation input/output from MT?
>There are several ways to do system sim with software:
>- behavi{*filter*}C code that interacts with VHDL simulator
>    (i.e. you application software is run, and whenever it accesses
>    a hardware register, the C process is paused, the VHDL simulator
>    is invoked, and then the value read from VHDL hardware register
>    is returned to the C process).
>    MTI can't do this; I've talked to them about it.

this is what i'd like to do. seems like some sort of api thru OLE or
DDE could accomplish this in the PC world. You keep the simulator and
software running as independent tasks, and the software uses the api
to read/write registers in the MTI HW model.

Quote:
>- C code, running as a subroutine to the VHDL simulator.
>    MTI can do this.  You can model software things that are totally
>    re-entrant, or you need to create registers to keep track of your
>    execution point in your C code, if you wish to return to the same
>    place you left off.  You can model CPUs in this way, by having
>    a progam-counter, etc.
>    MTI can do this; I have used a model from ARM to simulate hardware
>    and software working together.

can you post/email this for me?

Quote:
>- C code and simulator interacting via data files
>    This is problematical: how do you pause the entire VHDL simulator,
>    while waiting for your C code to process the VHDL output, and present
>    new input to the VHDL simulator?

it seemed pretty painful to me as well.. i was thinking there was some
way to set up breakpoints with mt, where you hit a bp, let sw create a
stimulus file, read the file with textio, mt writes the response in
another file and sets another bp,  sw reads that file....and so on.

Quote:
>The best/cleanest approach is to implement true inter-process communication
>between the VHDL simulation process and the C process.  Vantage does this;
>MTI doesn't (but MTI can work for some cases).
>I did a paper on this, at PLD-con 1995.

i can't find my copy of  the proceedings..do you have a postscript
file you could email/post?
Quote:
>Hope this helps,
>Erik Jessen



Fri, 13 Mar 1998 03:00:00 GMT  
 Testing HW/SW Integration with Model Tech

Quote:

>Has anyone tried to test hardware/software integration by developing a
>VHDL model of their hardware, and using MT to simulate the HW while
>the software is interacting with the simulation input/output from MT?

If you are using C or C++ code, ASC has a solution called VIOOL. It lets
you do a system level cosimulation of the hardware and the software. For
more information check the Web-page http://www.ascinc.com/viool.html
or send me an email.

  Ir. Casper B. Stoel                   Alternative System Concepts Inc.

  URL  : http://www.ascinc.com     tel (603) 437-2234 fax (603) 437-2722



Fri, 13 Mar 1998 03:00:00 GMT  
 Testing HW/SW Integration with Model Tech

Quote:



>>Has anyone tried to test hardware/software integration by developing a
>>VHDL model of their hardware, and using MT to simulate the HW while
>>the software is interacting with the simulation input/output from MT?

{snip}

Quote:
>The best/cleanest approach is to implement true inter-process communication
>between the VHDL simulation process and the C process.  Vantage does this;

Saw a demo of Eaglei (EagleIntegrator) at Euro-DAC which links VHDL and
software (C) simulation environments (Its a spin-off of the Vantage tool,
Co-Designer).

Looked good - full access to both VHDL & software debugging environments -
control of the system simulation from either or both simulation tools via
breakpoints etc.
Also showed cross-platform co-simulation linking PC Microsoft Visual C++ with
workstation Vantage VHDL simulator.
Fast too!

Only disadvantages seem to be support for Viewlogic VHDL tools only at the
moment (so no MTI), and current limited choice of processor models.

B.
_____________________________________________________________

"It's been lonesome in the saddle since the horse died"



Sat, 14 Mar 1998 03:00:00 GMT  
 
 [ 5 post ] 

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