minimum delay for Register-to-Register path in DC 
Author Message
 minimum delay for Register-to-Register path in DC

 From the manual, Synopsys Design Compiler uses the following
 equations to derive constraints for minimum and maximum delays on
 register-to-register paths :

    max_delay : (Tcapture - Tlauch) - setup
 ** min_delay : (Tcapture - Tlauch) + hold

 I can understand "max_delay". It's so simple.
 But for min_delay, I can't.

 Plz tell me what does that mean ?
 Thanks in advance

Taekeun Hwang
ASIC Design Engineer  [Seodu InChip ASIC Design Center]

Homepage     : http://www.*-*-*.com/ ; My ASIC page : http://www.*-*-*.com/

Mon, 14 Apr 2003 13:26:13 GMT  
 minimum delay for Register-to-Register path in DC
Hi Tae-Keun

               _____       _____
launch:   ____|     |_____|     |_____
 active edge: ^           A

             B____      _____       _____
capture:    _|    |____|     |_____|     |_____
 first capture:        ~

First The synthesis tool defines the related edges at
launching and capturing register. Data launched at a launch
edge ^ needs to be captured reliably (by default) by the very
active edge at the capture register ~. This relations ship
is being defined based on the ideal clock waveform you define,
without applying (at this point) any clock uncertainty or
network delay, for further calculation however everything you
define will be applied.

Based on the actual arrival time of these edges it finds out
the min and max delay for reliable capture:

No the synthesis tool works on setup relation ship. Data needs
to be valid at the data pin of the capture register slightly
before edge ~. This is what defines the max delay:

    max_delay : (Tcapture,~ - Tlauch,^) - setup
     delay should always be smaller then this.

The next thing it checks is the hold relationship; it does this by
actually checking two things:

1. Data launched at next edge A does not interfere with the
   capture used above(~)
2. Data launched at the actual launch (^) does not interfere
   with the previous capture at B.

Not interfering means that the data at the datapin of the capture
register does not start changing until some time after the edge:

1.   min_delay : (Tcapture,~ - Tlauch,A) + hold

2.   min delay : (Tcapture,B - Tlaunch,^) + hold
      min delay should always be larger then this


Synopsys (Northern Europe) Ltd.        phone:  +44 118 965 1176
Imperium, Imperial Way                   fax:  +44 118 975 0081

Mon, 14 Apr 2003 03:00:00 GMT  
 [ 2 post ] 

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