AZ-PHZ ASIC/FPGA designer with Verilog/VHDL. 
Author Message
 AZ-PHZ ASIC/FPGA designer with Verilog/VHDL.

This is a Senior level position needed. Please send me your resume to be
consider for this Senior Level position in an amazing company with good
benefits.  Pay is DOE and negociable.

Senior Engineer

ASIC Design
Education Required:
BS/MS in Electrical or Computer Engineering
3+ years experience
Digital Subsystem/ASIC/FPGA detailed logic design
Synthesiable VHDL/Verilog model design
Scripts and utilities development
Provide sales support
Ability to express logic in synthesizable VHDL or verilog
Firm understanding of the transformation go RTL code into gates
ASIC or FPGA design experience
Understanding of high-speed and sub-micron design issues
Excellent analytical and communication skills
Highly motivated self starter, well organized
Solaris or Windows-NT
Test complier
Fault Grading
Test generation
Firmware / Assembly
Digital PLL design
Clock tree Design
DMA design
FIFO design
Bus interface design
Datapump design

>100k gates

Sub-miron experience
FPGA - Xilina or Altera

Mon, 25 Aug 2003 03:38:14 GMT  
 [ 1 post ] 

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