character to STD_LOGIC_VECTOR 
Author Message
 character to STD_LOGIC_VECTOR

I use VHDL and a xilinx FPGA to adress a 4x20 dot-matrix (text-)
display. The HD44780 controller on the display understands ASCII code (8
bit) but I have to use a STD_LOGIC_VECTOR (7 downto 0) to adress the
display.
As the ASCII code is internally used to represent the type CHARACTER, is
there a way to convert Character to STD_LOGIC_VECTOR?

Thanks

Matthias



Fri, 31 Jan 2003 03:00:00 GMT  
 character to STD_LOGIC_VECTOR
Assuming you can use the numeric std
package and if you have a compliant
tool-set, you can do.

    use ieee.numeric_std.all ;
    ...
    signal myvec : std_logic_vector(7 downto 0) ;
    signal mychar : character ;        -- This is your character
    ...
    myvec <= std_logic_vector(to_unsigned(natural(character'pos(mychar)), 8)) ;

If your toolset does not support the 'pos attribute
then you may have to use a look-up table to map a character
to an integer (or directly to a std_logic_vector). From a
synthesis point of view, this should produce no logic at all.
Note that some compilers only support 7-bit ascii but the
code above should work for both 7 and 8-bit ascii.

Regards,
Haneef
www.symphonyeda.com


Quote:
> I use VHDL and a xilinx FPGA to adress a 4x20 dot-matrix (text-)
> display. The HD44780 controller on the display understands ASCII code (8
> bit) but I have to use a STD_LOGIC_VECTOR (7 downto 0) to adress the
> display.
> As the ASCII code is internally used to represent the type CHARACTER, is
> there a way to convert Character to STD_LOGIC_VECTOR?

> Thanks

> Matthias



Fri, 31 Jan 2003 03:00:00 GMT  
 character to STD_LOGIC_VECTOR

Quote:

> Assuming you can use the numeric std
> package and if you have a compliant
> tool-set, you can do.

>     use ieee.numeric_std.all ;
>     ...
>     signal myvec : std_logic_vector(7 downto 0) ;
>     signal mychar : character ;        -- This is your character
>     ...
>     myvec <= std_logic_vector(to_unsigned(natural(character'pos(mychar)), 8)) ;

I tried that, but Synopsys FPGA Express doesn't seem to support the 'pos attribute,

I get the error message:
Error   L59/C0 : #0 Error: Attribute  with arguments 'POS is not supported for
synthesis  on line 59  (VHDL-2151)

Quote:

> If your toolset does not support the 'pos attribute
> then you may have to use a look-up table to map a character
> to an integer (or directly to a std_logic_vector). From a
> synthesis point of view, this should produce no logic at all.
> Note that some compilers only support 7-bit ascii but the
> code above should work for both 7 and 8-bit ascii.

I tried something like this:

function CHAR2VEC2(CHAR: in CHARACTER)
  return STD_LOGIC_VECTOR is

  begin
   case CHAR is
    when 'A' => return "01000001";
    when 'B' => return "01000010";
    .....
   ..etc...
  ......
   end case;

It works, but I have to type in all ASCII characters. Is there another way to do
it?

Regards

Matthias.



Fri, 31 Jan 2003 03:00:00 GMT  
 character to STD_LOGIC_VECTOR
Quote:
>display. The HD44780 controller on the display understands ASCII code (8
>bit) but I have to use a STD_LOGIC_VECTOR (7 downto 0) to adress the
>display.
>As the ASCII code is internally used to represent the type CHARACTER, is
>there a way to convert Character to STD_LOGIC_VECTOR?

You can use the conversion routine built-in the std_logic_TextIO package.  Here
is an example (not tested, but should work).
  constant Strg_c : String := "1234";
  variable L_v : line;
  variable Std_v : std_logic_vector(3 downto 0);

 L_v := new String'(Strg_c);  -- does not have to be a constant.
-- can do new string'(Var);
Read(L_v,   Std_v); -- std_logic_textio.read
deallocate(L_v); -- keep clean !

------------------------------------------------------
VhdlCohen Training, Consulting, Verification

http://www.vhdlcohen.com/
Author of following textbooks:
VHDL Coding Styles and Methodologies, 2nd Edition,
  isbn 0-7923-8474-1 Kluwer Academic Publishers, 1999
VHDL Answers to Frequently Asked Questions, 2nd Edition,
  isbn 0-7923-8115-7 Kluwer Academic Publishers, 1998
------------------------------------------------------

Quote:
>>...xilinx FPGA to adress a 4x20 dot-matrix (text-)



Fri, 31 Jan 2003 03:00:00 GMT  
 character to STD_LOGIC_VECTOR

Quote:


> > Assuming you can use the numeric std
> > package and if you have a compliant
> > tool-set, you can do.

> >     use ieee.numeric_std.all ;
> >     ...
> >     signal myvec : std_logic_vector(7 downto 0) ;
> >     signal mychar : character ;        -- This is your character
> >     ...
> >     myvec <= std_logic_vector(to_unsigned(natural(character'pos(mychar)), 8)) ;

> I tried that, but Synopsys FPGA Express doesn't seem to support the 'pos attribute,

> I get the error message:
> Error   L59/C0 : #0 Error: Attribute  with arguments 'POS is not supported for
> synthesis  on line 59  (VHDL-2151)

> > If your toolset does not support the 'pos attribute
> > then you may have to use a look-up table to map a character
> > to an integer (or directly to a std_logic_vector). From a
> > synthesis point of view, this should produce no logic at all.
> > Note that some compilers only support 7-bit ascii but the
> > code above should work for both 7 and 8-bit ascii.

> I tried something like this:

> function CHAR2VEC2(CHAR: in CHARACTER)
>   return STD_LOGIC_VECTOR is

>   begin
>    case CHAR is
>     when 'A' => return "01000001";
>     when 'B' => return "01000010";
>     .....
>    ..etc...
>   ......
>    end case;

> It works, but I have to type in all ASCII characters. Is there another way to do
> it?

> Regards

> Matthias.

You can create a package and declare a constant that performs the
conversion:

library IEEE;
use IEEE.STD_LOGIC_1164.all;

package CHAR2STD is

  subtype WORD is STD_LOGIC_VECTOR(7 downto 0);
  type T is array(CHARACTER range NUL to DEL) of WORD;
  constant CHAR2STD: T;

end CHAR2STD;

package body CHAR2STD is

  constant CHAR2STD: T :=
    ("0000000", "0000001", "0000010", "0000011",
     "0000100", "0000101", "0000110", "0000111",
     "0001000", "0001001", "0001010", "0001011",
     "0001100", "0001101", "0001110", "0001111",
     "0010000", "0010001", "0010010", "0010011",
     "0010100", "0010101", "0010110", "0010111",
     "0011000", "0011001", "0011010", "0011011",
     "0011100", "0011101", "0011110", "0011111",
     "0100000", "0100001", "0100010", "0100011",
     "0100100", "0100101", "0100110", "0100111",
     "0101000", "0101001", "0101010", "0101011",
     "0101100", "0101101", "0101110", "0101111",
     "0110000", "0110001", "0110010", "0110011",
     "0110100", "0110101", "0110110", "0110111",
     "0111000", "0111001", "0111010", "0111011",
     "0111100", "0111101", "0111110", "0111111",
     "1000000", "1000001", "1000010", "1000011",
     "1000100", "1000101", "1000110", "1000111",
     "1001000", "1001001", "1001010", "1001011",
     "1001100", "1001101", "1001110", "1001111",
     "1010000", "1010001", "1010010", "1010011",
     "1010100", "1010101", "1010110", "1010111",
     "1011000", "1011001", "1011010", "1011011",
     "1011100", "1011101", "1011110", "1011111",
     "1100000", "1100001", "1100010", "1100011",
     "1100100", "1100101", "1100110", "1100111",
     "1101000", "1101001", "1101010", "1101011",
     "1101100", "1101101", "1101110", "1101111",
     "1110000", "1110001", "1110010", "1110011",
     "1110100", "1110101", "1110110", "1110111",
     "1111000", "1111001", "1111010", "1111011",
     "1111100", "1111101", "1111110", "1111111");

end CHAR2STD;

and then convert any CHARACTER like this:

use LIB.CHAR2STD.all;

...

A <= CHAR2STD(C);

Regards,
--
Renaud Pacalet, ENST / COMELEC, 46 rue Barrault 75634 Paris Cedex 13



Sun, 02 Feb 2003 03:00:00 GMT  
 character to STD_LOGIC_VECTOR
Sorry, I forgot 1 bit left in my constant. This should be OK:

library IEEE;
use IEEE.STD_LOGIC_1164.all;

package CHAR2STD is

  subtype WORD is STD_LOGIC_VECTOR(7 downto 0);
  type T is array(CHARACTER range NUL to DEL) of WORD;
  constant CHAR2STD: T;

end CHAR2STD;

package body CHAR2STD is

  constant CHAR2STD: T :=
    ("00000000", "00000001", "00000010", "00000011",
     "00000100", "00000101", "00000110", "00000111",
     "00001000", "00001001", "00001010", "00001011",
     "00001100", "00001101", "00001110", "00001111",
     "00010000", "00010001", "00010010", "00010011",
     "00010100", "00010101", "00010110", "00010111",
     "00011000", "00011001", "00011010", "00011011",
     "00011100", "00011101", "00011110", "00011111",
     "00100000", "00100001", "00100010", "00100011",
     "00100100", "00100101", "00100110", "00100111",
     "00101000", "00101001", "00101010", "00101011",
     "00101100", "00101101", "00101110", "00101111",
     "00110000", "00110001", "00110010", "00110011",
     "00110100", "00110101", "00110110", "00110111",
     "00111000", "00111001", "00111010", "00111011",
     "00111100", "00111101", "00111110", "00111111",
     "01000000", "01000001", "01000010", "01000011",
     "01000100", "01000101", "01000110", "01000111",
     "01001000", "01001001", "01001010", "01001011",
     "01001100", "01001101", "01001110", "01001111",
     "01010000", "01010001", "01010010", "01010011",
     "01010100", "01010101", "01010110", "01010111",
     "01011000", "01011001", "01011010", "01011011",
     "01011100", "01011101", "01011110", "01011111",
     "01100000", "01100001", "01100010", "01100011",
     "01100100", "01100101", "01100110", "01100111",
     "01101000", "01101001", "01101010", "01101011",
     "01101100", "01101101", "01101110", "01101111",
     "01110000", "01110001", "01110010", "01110011",
     "01110100", "01110101", "01110110", "01110111",
     "01111000", "01111001", "01111010", "01111011",
     "01111100", "01111101", "01111110", "01111111");

end CHAR2STD;

Regards,
--
Renaud Pacalet, ENST / COMELEC, 46 rue Barrault 75634 Paris Cedex 13



Sun, 02 Feb 2003 03:00:00 GMT  
 
 [ 6 post ] 

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