Verilog beginner trying to implement pipelining 
Author Message
 Verilog beginner trying to implement pipelining

Hi,

I'm a Verilog beginner trying to implement a
pipelined MIPS model with full bypassing and a
single branch delay slot.  Is there someone out
there who'll volunteer to see my code and tell me
what I'm doing wrong, because it's not working?

Thanks.

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Before you buy.



Wed, 26 Mar 2003 03:00:00 GMT  
 Verilog beginner trying to implement pipelining
Whats not working?
Quote:

> Hi,

> I'm a Verilog beginner trying to implement a
> pipelined MIPS model with full bypassing and a
> single branch delay slot.  Is there someone out
> there who'll volunteer to see my code and tell me
> what I'm doing wrong, because it's not working?

> Thanks.

> Sent via Deja.com http://www.deja.com/
> Before you buy.



Thu, 27 Mar 2003 03:00:00 GMT  
 
 [ 2 post ] 

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