xnf to Verilog translator 
Author Message
 xnf to Verilog translator

I am looking for a PD XININX xnf to Verilog (structural)
translator.  I would appreciate if someone can help me
out.  If anyone knows a way to generate an EDIF netlist
from Workview without having the netlister netlisting
XILINX primitives such as delay, that will work also.

Thanks in advance.

Jae Cho



Mon, 30 Dec 1996 23:10:28 GMT  
 
 [ 1 post ] 

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