Hi everybody,

Is someone can try to explain me which are the difference between VHDL
and VERILOG. Historic of these languages...

Thanks.
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I'll give it a quick shot....

VHDL was developed by the US D.o.D. (or they had it developed) in order
to standardize a way to describe VLSI chips in an HDL.  Or something like that.

Verilog HDL was developed as a proprietary language (I forgot the name of the
original company - was it Verilog?) which was then bought up by Cadence and
made open to the public.

You could say that VHDL is like C in that pretty much everything is open
to abuse.  Very little besides syntax, structure, and scheduling is predefined,
therefore a lot of stuff, like signal types and functions, needs to be defined
explicitly.  Since this could be pretty chaotic and no designer really wants
to do this, there are quite a few packages that contain the appropriate
base for doing design.  There are different standard packages (e.g. IEEE-xxx)
that are supported by the simulators and synthesizers.

On the other hand, Verilog is like Pascal in that you can do much of the stuff
you can do in VHDL (with less code), but you have nowhere near the flexibility
since a lot of stuff is predefined and cannot be changed.  (Funnily enough,
Verilog code resembles C code more....)

There are a lot more differences, but the basic argument is that Verilog is
generally quicker and easier to write at the cost of being tied down by its
strict rules.  (Increased degrees of flexibility are not free.)

says...

"Automated Integrated Design Systems" which was later renamed as
"Gateway Design Automation Inc".

A brief history of Verilog and Verilog PLI can be found at:

http://www.angelfire.com/ca/verilog/history.html

--
=-=-= 100% pure Verilog PLI - go, get it ! =-=-=
 Principles of Verilog PLI -By- Swapnajit Mittra
 Kluwer Academic Publishers. ISBN: 0-7923-8477-6
 http://www.angelfire.com/ca/verilog/

Automated Integrated Design Systems (AIDS) was founded a few months before the
disease was named. They changed their name to Gateway pretty quickly
after that happen.

I am reminded of the DAC design off a few years ago for a simple up
down counter circuit. All the Verilog designers failed miserably to
get their designs to work. Where as all the VHDL guys got their
designs to work easily & on time.

Or did I just get this all the wrong way around, nuh

If this is the famous up-by-5 down-by-3 counter challenge [or the other
way around] IIRC it was the Verilog designers that - mostly - got it
written, simulated, synth'ed, & meeting the spec in the alotted time. I
don't think any of the VHDL ones did, RSI probably slowed them down
significantly.

From the Monty python sketch
"It was awful, he used sarcasm on me,...."