Anyone uses perl to driver verilog stimulus ? 
Author Message
 Anyone uses perl to driver verilog stimulus ?

I am wondering if anyone has used perl as a stimulus driver for verilog.
How do you implement the perl/verilog interface ?

I would like to have a user code in perl (master mode).  I also would
like to use verilog callback to provide concurrency (slave mode).  I
want my perl routine to implement split transcations and deal with the
dispatching of requests to a queue if it's not full.  Otherwise, wait
until the queue is not full.  Currently there is no way to advance time
from perl unless I return control back to simulator.  Here's a sample
code:
        $addr = 0xf0;
        $data = 0xdeadbeef;
        wr $addr, $data; # if queue not full, send wr req
        rd $addr, $data; # send rd req and check data when resp comes

The wr routine cannot complete until the req has been accepted.
Therefore the routine must wait for an ack from HDL.  I want the user
code to execute sequentially.

The bottom line is I want the Perl code to be able to advance time and
still do call-back.  I implement the routines as tasks but then I don't
have perl data structues and other wonderful constructs.

I hope this is not confusing.

Thanks in advance



Sun, 01 Nov 1998 03:00:00 GMT  
 Anyone uses perl to driver verilog stimulus ?

Quote:

> I am wondering if anyone has used perl as a stimulus driver for verilog.
> How do you implement the perl/verilog interface ?

I use Forth as stimulus driver. However, I don't generate simuli on the fly, but
a list of stimuli in advance, and then use Verilog to feed these stimuli into
the tested module (and eventually compare against the precomputed results). This
driver looks about like this:

// test floating point multiplication

`define L  [0:l-1]

module main;
   parameter l=64, delay=10;
   reg `L a, b, d, e, f, g;
   wire `L c;
   reg clock;
   reg [0:3*l-1] mem [0:255];
   reg [0:7] i;

   fadd float(clock, 4'b0000, a, b, 118'b0, 2'b00, c);

   initial
    begin
       $readmemh("fpu.input", mem);
       clock = 1'b1;
       i = 1;
       { a, b, d } = mem[0];
       #delay clock = 0;
       #delay repeat(256)
       begin
          { e, f, g } = { a, b, d};
          { a, b, d } = mem[i];
          clock = 1;
          #delay clock = 0;
          #delay $display("%x+%x=%x (%x,diff %x) %0d", e, f, c, g, g-c, $time);
          i=i+1;
       end
    end

endmodule /* main */

Hope this helps.

--
Bernd Paysan
"Late answers are wrong answers!"
http://www.informatik.tu-muenchen.de/~paysan/



Fri, 06 Nov 1998 03:00:00 GMT  
 Anyone uses perl to driver verilog stimulus ?

One method we use is sockets and PLI. The socket stuff you need is built in
to perl. The verilog end needs special PLI. Please don't ask for the code.

                                        John Williams



Wed, 11 Nov 1998 03:00:00 GMT  
 Anyone uses perl to driver verilog stimulus ?


Quote:

>I am wondering if anyone has used perl as a stimulus driver for verilog.
>How do you implement the perl/verilog interface ?

I gave a tutorial on this at this year's International Verilog Conference.  I
cowrote a paper on this as well, also presented at IVC.  If you are
interested, I can make arrangements to get you the paper and slides.

--
Elliot Mednick                                      P.O. Box 150
Wellspring Solutions, Inc.                          Sutton, MA.  01590
                                                    (508) 865-7271



Sun, 15 Nov 1998 03:00:00 GMT  
 Anyone uses perl to driver verilog stimulus ?

I am interested in reading this paper. Is it also available on-line ?

Regards,
Vineet.
--
-Vineet
* Vineet Pancholi           * Microchip Technology Inc. * Voice:(602)786-7461 *
* Product Test Engineer     * 2355 W. Chandler Blvd.    * Fax  :(602)917-4005 *



Sun, 22 Nov 1998 03:00:00 GMT  
 
 [ 5 post ] 

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