Free Xilinx Simulation Interface for Verilog 
Author Message
 Free Xilinx Simulation Interface for Verilog

A free Xilinx to Verilog interface program is available for anonymous
ftp from punisher.caltech.edu in pub/dank/xnf2ver.tar.Z.

This program is not really ready for prime time, but I thought I'd
make the sources available (with the permission of M J Colley) so
others could play with & possibly improve it.
I think I made it a lot more solid than it was, but it still can't handle
real world designs yet.

Here's part of the README:

                  XNF to Verilog Translator

                        M J Colley
                Department of Computer Science
                    University of Essex
                      Wivenhoe Park
                        Colchester
                      Essex CO4 3SQ
                           UK


Disclaimer:

This program was written by a postgraduate student as part of his M.Sc
course, it was designed to form part a larger system operating with the
Cadence Edge 2.1 framework. This should be bourne in mind when considering
the construction and/or operation of the program.

Warrenty:

This source code is provided with NO warrenty whatsoever. It is left up to
the user to satisfy themselves that the output produced is correct.

Copyright:

The source code is copyright of the Department of Computer Science, University
of Essex, UK. You are free to use and/or modify the code to your own needs. You
are asked to inform the copyright holder should you distribute this code to a
third party.

Contents:

This archieve contains the following:

  The XNF to Verilog translator source code and makefile.
  Verilog models for the D_FF and LATCH flipflops used by the translator.
  CLB and IOB timing data file.
  SED scripts for setting the model timing and the script generator program.
  A postprocessor to set the delay timing of the nets.

...



Wed, 12 Jul 1995 02:48:41 GMT  
 
 [ 1 post ] 

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