Free Xilinx Simulation Interface for Verilog 
Author Message
 Free Xilinx Simulation Interface for Verilog

A free Xilinx to Verilog interface program is available for anonymous
ftp from in pub/dank/xnf2ver.tar.Z.

This program is not really ready for prime time, but I thought I'd
make the sources available (with the permission of M J Colley) so
others could play with & possibly improve it.
I think I made it a lot more solid than it was, but it still can't handle
real world designs yet.

Here's part of the README:

                  XNF to Verilog Translator

                        M J Colley
                Department of Computer Science
                    University of Essex
                      Wivenhoe Park
                      Essex CO4 3SQ


This program was written by a postgraduate student as part of his M.Sc
course, it was designed to form part a larger system operating with the
Cadence Edge 2.1 framework. This should be bourne in mind when considering
the construction and/or operation of the program.


This source code is provided with NO warrenty whatsoever. It is left up to
the user to satisfy themselves that the output produced is correct.


The source code is copyright of the Department of Computer Science, University
of Essex, UK. You are free to use and/or modify the code to your own needs. You
are asked to inform the copyright holder should you distribute this code to a
third party.


This archieve contains the following:

  The XNF to Verilog translator source code and makefile.
  Verilog models for the D_FF and LATCH flipflops used by the translator.
  CLB and IOB timing data file.
  SED scripts for setting the model timing and the script generator program.
  A postprocessor to set the delay timing of the nets.


Wed, 12 Jul 1995 02:48:41 GMT  
 [ 1 post ] 

 Relevant Pages 

1. Xilinx post route simulation

2. Functional VHDL Simulation Problem with Xilinx Coregen Async FIFOs with Modelsim

3. Xilinx:Post syn. simulation

4. Leonardo/Modelsim/Xilinx post synthesis simulation (VHDL)

5. Post Synthesis Simulation in Synopsys for Xilinx XL4000 FPGA

6. Glitches in timing simulation of Xilinx FPGAs with Synopsys

7. Xilinx XNF to VHDL for Simulation

8. More xilinx webpack verilog questions: always @(clock) legal?

9. Mixed VHDL and Verilog with Xilinx ISE

10. Xilinx/Altera "behavioral" verilog

11. Choosing a verilog synthesis tool (Altera/Xilinx)

12. Verilog model of Xilinx macro in VHDL Testbench fails


Powered by phpBB® Forum Software