code coverage 
Author Message
 code coverage

hello:

Is anyone aware of a tool that accepts testcases written in C
language in order to measure code coverage.?
The design is in Verilog, but the testcases are in C language.

I am aware of the code coverage tools that measure the code
coverage when the design is in Verilog and the testcases are in
verilog too.

-Thank you very much

Sent via Deja.com http://www.*-*-*.com/
Before you buy.



Mon, 24 Feb 2003 07:45:08 GMT  
 code coverage
Someone correct me if I'm wrong, but as long as you simulate your design
and testbench in a Verilog simulator, then your average code coverage
tool should be usable. The code coverage tool is tracking execution of
the Verilog DUT in simulation. As long as your testbench causes your
Verilog to execute, I don't think you should have a problem.

You're not wanting to run code coverage on your testbench, are you?

-cb

Quote:

> hello:

> Is anyone aware of a tool that accepts testcases written in C
> language in order to measure code coverage.?
> The design is in Verilog, but the testcases are in C language.

> I am aware of the code coverage tools that measure the code
> coverage when the design is in Verilog and the testcases are in
> verilog too.

> -Thank you very much

> Sent via Deja.com http://www.deja.com/
> Before you buy.



Mon, 24 Feb 2003 22:52:59 GMT  
 code coverage

Chris is right on here.

While code coverage tools allow you to measure code coverage of your
testbench if the testbench is written in Verilog, most people turn
that off and just focus on getting good coverage of the part of the
design that is to be synthesized.

If some aspect of the functional measurement of goodness of your
design is coded in your testbench, then it may be useful to measure
coverage over that section of your design as well.  

Likely much better is to use something like the Specman functional
coverage feature, which allows you to look at all sorts of crosses
over the values of various inputs when outputs (or internal state
nodes) had various values.

Quote:

> Someone correct me if I'm wrong, but as long as you simulate your design
> and testbench in a Verilog simulator, then your average code coverage
> tool should be usable. The code coverage tool is tracking execution of
> the Verilog DUT in simulation. As long as your testbench causes your
> Verilog to execute, I don't think you should have a problem.

> You're not wanting to run code coverage on your testbench, are you?

> -cb


> > hello:

> > Is anyone aware of a tool that accepts testcases written in C
> > language in order to measure code coverage.?
> > The design is in Verilog, but the testcases are in C language.

> > I am aware of the code coverage tools that measure the code
> > coverage when the design is in Verilog and the testcases are in
> > verilog too.

> > -Thank you very much

> > Sent via Deja.com http://www.deja.com/
> > Before you buy.

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Tue, 25 Feb 2003 07:13:02 GMT  
 
 [ 3 post ] 

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