SystemC 
Author Message
 SystemC

I am a new user of Verilog (learning) but in the mean time
found out about SystemC as a higher level language for
simulation. I would appreciate any comments from
experience on:
1) The usefulness and usability of SystemC
2) How much of Verilog knowledge does one need before moving on to SystemC
3) Has anyone done full system development just or mostly using SystemC

thanks in advance
yohannes



Tue, 26 Aug 2003 23:43:03 GMT  
 SystemC

You may want to take a look at the CynApps language called Cynlib. I think you
will find that it has a cleaner C++ HDL implementation. You can compare Cynlib
with SystemC, by looking at examples in the Cynapps WEB page below.

http://chronos.cynapps.com/bres-cgi-bin/show_systemc.pl

The corresponding SystemC examples are found in the 1.2 Beta release.

We are currently using Cynlib to design a 25 million transistor ASIC.

Robert

Quote:

> I am a new user of Verilog (learning) but in the mean time
> found out about SystemC as a higher level language for
> simulation. I would appreciate any comments from
> experience on:
> 1) The usefulness and usability of SystemC
> 2) How much of Verilog knowledge does one need before moving on to SystemC
> 3) Has anyone done full system development just or mostly using SystemC

> thanks in advance
> yohannes

  rac.vcf
< 1K Download


Wed, 27 Aug 2003 05:52:03 GMT  
 SystemC

Quote:

> I am a new user of Verilog (learning) but in the mean time
> found out about SystemC as a higher level language for
> simulation. I would appreciate any comments from
> experience on:
> 1) The usefulness and usability of SystemC
> 2) How much of Verilog knowledge does one need before moving on to SystemC

None, you just need to know how to program in C++.
Quote:

> 3) Has anyone done full system development just or mostly using SystemC

> thanks in advance
> yohannes



Fri, 29 Aug 2003 18:17:16 GMT  
 
 [ 3 post ] 

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