parameter redefinition II 
Author Message
 parameter redefinition II

Hello again,

Thanks to everyone who replied to my first message but I
didn't quite get the answers I was after.  Must have
phrased the question wrong, so I'll try again.

A better way of illustrating what I'm looking for is as
a means of redefining a simulation's parameters while that
simulation is operating, and to do so as a reaction to a
change in the system (some input, for example).  

For instance, I am modelling a memory device that can
operate under both 5.0V and 3.3V supply.  Due to the nature
of things it will operate faster under the 5.0V supply than
under the 3.3V and will hence have different timing parameters
for the mode of operation.  In the simulation
I want to be able to start at 5.0V for my memory device, and then
at some random time reset it and power it up again with only a 3.3V
supply.  
How do I write the Verilog code to allow me to, on the fly, change
the timing parameters?

--
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Terence Gilhuly

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Wed, 01 Jan 1997 01:17:36 GMT  
 parameter redefinition II

g> Hello again, Thanks to everyone who replied to my first message but
g> I didn't quite get the answers I was after.  Must have phrased the
g> question wrong, so I'll try again.

g> A better way of illustrating what I'm looking for is as a means of
g> redefining a simulation's parameters while that simulation is
g> operating, and to do so as a reaction to a change in the system
g> (some input, for example).

g> For instance, I am modelling a memory device that can operate under
g> both 5.0V and 3.3V supply.  Due to the nature of things it will
g> operate faster under the 5.0V supply than under the 3.3V and will
g> hence have different timing parameters for the mode of operation.
g> In the simulation I want to be able to start at 5.0V for my memory
g> device, and then at some random time reset it and power it up again
g> with only a 3.3V supply.  How do I write the Verilog code to allow
g> me to, on the fly, change the timing parameters?

Ok, in that case, realize that you can use variables to represent
delays.

I'd suggest you construct some thing in your simulation scaffolding
that provides a delay value, and use a rooted cross module reference
to access the value.  Make the value sensitive to your changing vcc,
and I think you have what you want:

module top
        real mem_dly; // All memory cells use this delay
        real vcc;     // Current VCC voltage

        initial begin
                vcc = 5.0;              
                ...
                #10000
                vcc = 3.3;
                ...
        end


                if (vcc == 5.0)
                        mem_dly = 2.6;
                else if (vcc == 3.3)
                        mem_dly = 3.2;
                else begin
                        $display("%g is an unsupported value for vcc",vcc);
                end

        end
endmodule

module mem(a, b);
        output a;
        input  b;
        not #(top.mem_dly) (a,b); // or whatever...

endmodule
--


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Thu, 02 Jan 1997 01:37:26 GMT  
 
 [ 2 post ] 

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