Pipelined Processor Clk 
Author Message
 Pipelined Processor Clk

Hi,

I am currently designing a 16-bit pipeline RISC processor in Verilog. I had
a question regarding the clocking of such a structure. Currently i have a
clock divider circuitry that i have use to generates clks of different
frequencies.

Now i use one clk lower Frequency to clk each stage of the pipeline and a
higher frequecy clk to CLK each of the steps within a particular stage of a
pipeline. Is this the best way to implement such a processor?

Are there any other methods of implementing the a Pipelined Processor.?
I have considered a Asynchronous structure, but besides that was wondering
if there are any other methods in the synchronous domain.

Thanks
Kartik



Tue, 30 Aug 2005 01:40:59 GMT  
 Pipelined Processor Clk
Hi!
I have designed a 32 bit RISC, and i do not understand why you require
different clock domains.
Can you explain your architecture a little bit, so that i can comment.

Rajkumar...

Quote:

> Hi,

> I am currently designing a 16-bit pipeline RISC processor in Verilog. I had
> a question regarding the clocking of such a structure. Currently i have a
> clock divider circuitry that i have use to generates clks of different
> frequencies.

> Now i use one clk lower Frequency to clk each stage of the pipeline and a
> higher frequecy clk to CLK each of the steps within a particular stage of a
> pipeline. Is this the best way to implement such a processor?

> Are there any other methods of implementing the a Pipelined Processor.?
> I have considered a Asynchronous structure, but besides that was wondering
> if there are any other methods in the synchronous domain.

> Thanks
> Kartik



Tue, 30 Aug 2005 15:14:14 GMT  
 
 [ 2 post ] 

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