ANNOUNCE: Free seminars on language-based FPGA design (UK) 
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 ANNOUNCE: Free seminars on language-based FPGA design (UK)

Next week we are hosting a series of regional seminars on VHDL and
Verilog based design for FPGA and CPLD devices using Viewlogic Workview
Office.

We will perform a complete design demo, from mixed schematic and VHDL
through to implementation in an FPGA. Although the demo will be VHDL
based (SpeedWave simulator + ViewSynthesis), we will be introducing the
Verilog flow (Chronologic VCS + ViewSynthesis) now available within the
Workview Office suite.

The technical level will be suitable for those wishing to transition
from schematic-based design, whether or not they are already using
Viewlogic tools. There will be no non-engineer presenting at any point.

The seminar locations are Bracknell - Tuesday 15th, Manchester Wed.
16th, Cambridge Thur. 17th, Edinburgh Fri. 18th.

Please email or call Caroline Hawkins if you wish to attend.
--
David Pashley                 <

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Sun, 26 Dec 1999 03:00:00 GMT  
 
 [ 1 post ] 

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