Read Shell Environment Variables (Strings) into Verilog-XL? 
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 Read Shell Environment Variables (Strings) into Verilog-XL?

How can I read in UNIX shell environment variables into Verilog?  Is there any
system tasks built-in in Verilog-XL for such purpose, besides recompiling with
PLI?

Actually, what I need is to set the path for output generated during simulation,
i.e. I need a way to pass a string into the Verilog code.

I tried using the Predefined Plus Options +define+ but it interpreted the value
as identifier instead of string.  For example,

        module my_test;

        initial
        begin
          $shm_open( `SHM_PATH );       // Macro to be expanded
          $shm_probe();
        end

        ...

        endmodule

and in shell prompt,

        > verilog +define+SHM_PATH=/tmp/anyuser my_test.v

The $shm_open system task expects string as argument, but Verilog treated
/tmp/anyuser as identifier instead of string.  I also tried enclosed the path
with double quotes and even escape-double quotes, but they didn't work either.

        > verilog +define+SHM_PATH="/tmp/anyuser" my_test.v
        > verilog +define+SHM_PATH=\"/tmp/anyuser\" my_test.v

I can't enlose the `SHM_PATH in Verilog using double quotes because it will
suppress the macro substitution.

        $shm_open( "`SHM_PATH" );     // Won't be expanded

So, if anyone knows how to get around with this problem, please kindly help me.
I appreciate it.

Thanks.

Hon-Chi Ng
Electrical and Computer Engineering Dept
Iowa State University



Mon, 10 Jul 2000 03:00:00 GMT  
 Read Shell Environment Variables (Strings) into Verilog-XL?

Quote:

>How can I read in UNIX shell environment variables into Verilog?  Is there
any
>system tasks built-in in Verilog-XL for such purpose, besides recompiling
with
>PLI?

>Actually, what I need is to set the path for output generated during
simulation,
>i.e. I need a way to pass a string into the Verilog code.

>I tried using the Predefined Plus Options +define+ but it interpreted the
value
>as identifier instead of string.  For example,

> module my_test;

> initial
> begin
>   $shm_open( `SHM_PATH ); // Macro to be expanded
>   $shm_probe();
> end

> ...

> endmodule

>and in shell prompt,

> > verilog +define+SHM_PATH=/tmp/anyuser my_test.v

>The $shm_open system task expects string as argument, but Verilog treated
>/tmp/anyuser as identifier instead of string.  I also tried enclosed the
path
>with double quotes and even escape-double quotes, but they didn't work
either.

> > verilog +define+SHM_PATH="/tmp/anyuser" my_test.v
> > verilog +define+SHM_PATH=\"/tmp/anyuser\" my_test.v

>I can't enlose the `SHM_PATH in Verilog using double quotes because it will
>suppress the macro substitution.

> $shm_open( "`SHM_PATH" ); // Won't be expanded

>So, if anyone knows how to get around with this problem, please kindly help
me.
>I appreciate it.

>Thanks.

>Hon-Chi Ng
>Electrical and Computer Engineering Dept
>Iowa State University

This is a shell issue, not a Verilog one.

Try:  verilog +define+SHM_PATH='\"/tmp/anyuser\"' my_test.v

That is, add a single quote after the = and and the very end of the plusarg.

                    -- Scott



Mon, 10 Jul 2000 03:00:00 GMT  
 Read Shell Environment Variables (Strings) into Verilog-XL?

: This is a shell issue, not a Verilog one.

Yes.  I have found it very helpful to look at the log file to
see just what Verilog got.  You want to see

        +define+SHMDIR=\"/abc/def\"

Many people have one or more shell scripts involved when they run

important.



Mon, 10 Jul 2000 03:00:00 GMT  
 
 [ 3 post ] 

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