Verilog - PLI passing args. 
Author Message
 Verilog - PLI passing args.

I am currently working on a project which requires an extensive use of PLI.

I am trying to get certain information form Verilog specs.
( data_paths, Active ports, Active nets , variables etc thru' pli)

This information is required to really get get the project off the ground.

while trying to pass arguments to get_paths or nets , compiler does not
complain , But in all cases it gives

Path is (NULL).

I think there is something wrong the way i pass args.

In Verilog specs I have called the task.
$get_path( Module_name, "in_port", "out_port");

and the function get_path is :

*****************************************************
#include "acc_user.h"

get_path()
{
handle path_handle, mod_handle, src_handle, dst_handle;

acc_initialize();

acc_configure(accDevelopmentVersion,"1.5a");

acc_configure(accEnableArgs,"acc_handle_modpath");

mod_handle = acc_handle_tfarg(1);
src_handle = acc_handle_tfarg(2);
dst_handle = acc_handle_tfarg(3);

path_handle=acc_handle_modpath(mod_handle,null,null,src_handle,dst_handle);

io_printf("path is %s \n", acc_fetch_fullname(path_handle));
acc_close();

Quote:
}

*****************************************************
Problem : In all cases it gives : path is (NULL)

I think I the problem lies in the way I pass args.

Any help is appreciated very much.

I also tries another route: To get args passes from a file: pathconn.dat
For this the function get_path looks like:

*****************************************************
#include <stdio.h>
#include "acc_user.h"
#define NAME_SIZE 256

get_path()

{
FILE *infile;
char  mod_name[NAME_SIZE], src_name[NAME_SIZE], dest_name[NAME_SIZE];
handle  path_handle, mod_handle;

acc_initialize();

acc_configure(accDevelopmentVersion,"1.5a");
acc_configure(accPathDelimStr,"_");

acc_configure(accEnableArgs,"acc_handle_modpath");

infile = fopen("pathconn.dat", "r");
while(fscanf(infile,"%s %s %s",mod_name, src_name, dest_name) !=EOF);

      {

mod_handle = acc_handle_object (mod_name);

path_handle = acc_handle_modpath(mod_handle, src_name, dest_name);

io_printf("path is %s \n", acc_fetch_fullname(path_handle));

Quote:
}

acc_close();

Quote:
}  

***********************************************************

In the file pathconn I have

fifo datain dataout  

ie.  Modulename pathsource path destination

But in all cases I keep getting path is (NULL).

Any help to get the path would be helpful.

This info on data is used to build the CDFG.



Tue, 07 May 1996 10:38:01 GMT  
 Verilog - PLI passing args.
There's lots that go wrong in the example you gave that you haven't shown,
for example, what are the arguments in the system call in verilog that you
use to call the PLI?

My suggestion is to simplify the problem, and use a good symbolic de{*filter*}.
My personal favorite is GDB from within an emacs window. You can't read
anything from the verilog object, but your own source should be fully
visible.

Hope this helps . . .

                                                John Williams



Sat, 11 May 1996 15:48:42 GMT  
 
 [ 2 post ] 

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