How to use synthesis tool to get gate level netlist only containing verilog basic gates 
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 How to use synthesis tool to get gate level netlist only containing verilog basic gates

The synthesis result cann't contain any macro-module in the library.
Only basic gates are available in the result.
Even flip-flop cann't be used.
How to do it with Synplify or BuildGates?

Thanks in advance.



Sat, 12 Nov 2005 18:38:11 GMT  
 
 [ 1 post ] 

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