synchronous reset/set or asynchronous reset/set 
Author Message
 synchronous reset/set or asynchronous reset/set

Quote:

> Hi,everyone:
> I have heared that it is better to use synchronous reset/set than to use
> asynchronous reset/set,
> Why?  And when I must use asynchronous reset/set, what do I need to be
> attention?
> Thanks
> Chenmin

--
The asynch reset is best used in a circuit when you want to reset on
power-on or to initialize the circuit as a whole. In the normal
operation of a circuit it is not good to use the async reset as part of
the logic function. This can cause difficulty in test and design
verification. For example, in performing timing analysis, a synchronous
reset can be verified to operate correctly. The async reset often causes
a combinat{*filter*}feedback loop which can no be analyzed for timing.

In general, designs should be totally synchronous unless you have a very
good reason.

Rick Collins


remove the XY to email me.



Sat, 07 Oct 2000 03:00:00 GMT  
 synchronous reset/set or asynchronous reset/set

Hi,everyone:
I have heared that it is better to use synchronous reset/set than to use
asynchronous reset/set,
Why?  And when I must use asynchronous reset/set, what do I need to be
attention?
Thanks
Chenmin



Sun, 08 Oct 2000 03:00:00 GMT  
 synchronous reset/set or asynchronous reset/set

Quote:

> Hi,everyone:
> I have heared that it is better to use synchronous reset/set than to use
> asynchronous reset/set,
> Why?  And when I must use asynchronous reset/set, what do I need to be
> attention?
> Thanks
> Chenmin

Asynchronous chip design should be avoided because:

- It complicates the static timing analysis
- It complicates the automatic scan test insertion
- It may lead to very risky race condition
- Automatic reoptimizing after layout is difficult and risky
- portability is not ensure

In fact all tools used in a design flow works very well when
the design is synchronous and MANY MANY problems appears when
the design is partially asynchronous.

A single clock, a single clock edge, no latch, no async
set/reset pins on FF, no internal bidir, no internal tri state,
no gated clock is a way for success.

With today technology, gates count is non longer an issue
(20000 g/mm2 in 0.35 um, 35000 g/mm2 in 0.25 um) so in my
opinion, there are no good reason at all to use the asynchronous
FF reset/set pins.

The only case where asynchronous reset/set may be tolerated is
for simulation power up where some/all FF async clear inputs
are tied together with a chip reset pin.

Bye



Sun, 08 Oct 2000 03:00:00 GMT  
 synchronous reset/set or asynchronous reset/set

Quote:


> > Hi,everyone:
> > I have heared that it is better to use synchronous reset/set than to use
> > asynchronous reset/set,
> > Why?  And when I must use asynchronous reset/set, what do I need to be
> > attention?
> > Thanks
> > Chenmin

> Asynchronous chip design should be avoided because:

> - It complicates the static timing analysis
> - It complicates the automatic scan test insertion
> - It may lead to very risky race condition
> - Automatic reoptimizing after layout is difficult and risky
> - portability is not ensure

> In fact all tools used in a design flow works very well when
> the design is synchronous and MANY MANY problems appears when
> the design is partially asynchronous.

> A single clock, a single clock edge, no latch, no async
> set/reset pins on FF, no internal bidir, no internal tri state,
> no gated clock is a way for success.

> With today technology, gates count is non longer an issue
> (20000 g/mm2 in 0.35 um, 35000 g/mm2 in 0.25 um) so in my
> opinion, there are no good reason at all to use the asynchronous
> FF reset/set pins.

> The only case where asynchronous reset/set may be tolerated is
> for simulation power up where some/all FF async clear inputs
> are tied together with a chip reset pin.

> Bye

All very good advice to ease the pain of chip design. If by synchronous
reset/set you mean that that you have pins on your FF's which will
reset/set your FF on an active edge of the clock then I would go one
stage further and suggest you avoid FF's of this type. If you require
your FF's to enter a particular state for a particular event, it is
better to do your design so that they are loaded via the D-input. The
reason I say this is that if your FF has reset/set pins which are
controlled via another FF (in the same or a different scan chain), it is
quite easy to reset/set that FF when running scan tests. Obviously the
quality of your test tool will determine if it can "understand" this
type of structure and make allowances for it.

Steve.
--
********************************************************************
* Steve Emm, Philips Semiconductors, Southampton, U.K.             *

* tel   : +44 1703 316361                 (fax  : +44 1703 316303) *
********************************************************************



Mon, 09 Oct 2000 03:00:00 GMT  
 synchronous reset/set or asynchronous reset/set

what if you take the reset pin of the chip, synchronize it using two dffs and the
connect the output to all the asynch reset inputs of all dffs ? Is this an OK use
of the asynch reset ?

Quote:


>> Hi,everyone:
>> I have heared that it is better to use synchronous reset/set than to use
>> asynchronous reset/set,
>> Why?  And when I must use asynchronous reset/set, what do I need to be
>> attention?
>> Thanks
>> Chenmin

>Asynchronous chip design should be avoided because:

>- It complicates the static timing analysis
>- It complicates the automatic scan test insertion
>- It may lead to very risky race condition
>- Automatic reoptimizing after layout is difficult and risky
>- portability is not ensure

>In fact all tools used in a design flow works very well when
>the design is synchronous and MANY MANY problems appears when
>the design is partially asynchronous.

>A single clock, a single clock edge, no latch, no async
>set/reset pins on FF, no internal bidir, no internal tri state,
>no gated clock is a way for success.

>With today technology, gates count is non longer an issue
>(20000 g/mm2 in 0.35 um, 35000 g/mm2 in 0.25 um) so in my
>opinion, there are no good reason at all to use the asynchronous
>FF reset/set pins.

>The only case where asynchronous reset/set may be tolerated is
>for simulation power up where some/all FF async clear inputs
>are tied together with a chip reset pin.

>Bye

muzo




Wed, 11 Oct 2000 03:00:00 GMT  
 synchronous reset/set or asynchronous reset/set

Quote:
> what if you take the reset pin of the chip, synchronize it using two dffs and the
> connect the output to all the asynch reset inputs of all dffs ? Is this an OK use
> of the asynch reset ?

This could be OK, see below for
more info (plus I have to add some lines to get the news server to
accept my message.. I hate when
I have to do that...)

Quote:

> >> Hi,everyone:
> >> I have heared that it is better to use synchronous reset/set than to use
> >> asynchronous reset/set,
> >> Why?  And when I must use asynchronous reset/set, what do I need to be
> >> attention?

> >Asynchronous chip design should be avoided because:

> >- It complicates the static timing analysis
> >- It complicates the automatic scan test insertion
> >- It may lead to very risky race condition
> >- Automatic reoptimizing after layout is difficult and risky
> >- portability is not ensure

> >In fact all tools used in a design flow works very well when
> >the design is synchronous and MANY MANY problems appears when
> >the design is partially asynchronous.

> >A single clock, a single clock edge, no latch, no async
> >set/reset pins on FF, no internal bidir, no internal tri state,
> >no gated clock is a way for success.

> >With today technology, gates count is non longer an issue
> >(20000 g/mm2 in 0.35 um, 35000 g/mm2 in 0.25 um) so in my
> >opinion, there are no good reason at all to use the asynchronous
> >FF reset/set pins.
> >Bye

> muzo

With regard to async and sync reset... In general as was mentioned above, its good
to have everything syncronous, but sometimes you run into situarions were you need
an async reset (if you don't have a clock, for instance), if you're doing a design
with multiple clocks, and some aren't always available (if you get a clock from
an external IO chip that doesn't provide clocks for some time after power up
for instance), you might need to use an asyncronos reset.  In anycase, 99.9% of the
time the reset pin of a FF (sync or async) should be connected to a chip reset line.

If you use the async reset line, and sync it to the clock ,  its ok, but scan can't
test those reset syncroniser flops well...(as was mentioned before, when the
active level of reset scans through them, it'll reset all the FF's connected to
it, but there are ways around this that aren't too painfull, like forcing the
reset output deasserted when in scan mode....).

There are times when you might want to functionally use the async reset line of a
FF (as a armable edge detector for instance..).  When your dealing with lots of
clocks in a design, you have to break the 'good design practices' rules sometimes.

But if you only do it when its absolutely necessary, it usually doesn't impact
DFT, too much (plus there's always partial scan...).

Ken



Sat, 14 Oct 2000 03:00:00 GMT  
 synchronous reset/set or asynchronous reset/set


...

Quote:
>> >Asynchronous chip design should be avoided because:

>> >- It complicates the static timing analysis
>> >- It complicates the automatic scan test insertion
>> >- It may lead to very risky race condition
>> >- Automatic reoptimizing after layout is difficult and risky
>> >- portability is not ensure

>> >In fact all tools used in a design flow works very well when
>> >the design is synchronous and MANY MANY problems appears when
>> >the design is partially asynchronous.

>> >A single clock, a single clock edge, no latch, no async
>> >set/reset pins on FF, no internal bidir, no internal tri state,
>> >no gated clock is a way for success.

>> >With today technology, gates count is non longer an issue
>> >(20000 g/mm2 in 0.35 um, 35000 g/mm2 in 0.25 um) so in my
>> >opinion, there are no good reason at all to use the asynchronous
>> >FF reset/set pins.

InterHDL has two new tools that help analyze and report clock and
asynchronoous design related problems: CheckIt and TestIt. For more

Eli

--
Eli Sternheim
interHDL, Inc.
4984 El Camino Real, Suite 210
Los Altos, CA. 94022-1433
phone: 650-428-4200
fax:   650-428-4201



Thu, 19 Oct 2000 03:00:00 GMT  
 
 [ 8 post ] 

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