Qualis Top-Down Design With Verilog Course: July 17-21
The next Qualis Top Down Design Using Verilog class is
scheduled for July 17-21 at Qualis Design Corporation in
Beaverton, Oregon, and will accommodate 10 students.
Qualis does not anticipate offering another Verilog class
until September.
Regards - Cliff Cummings
Qualis Training Schedule
------------------------
"A Comprehensive Introduction to Top Down Design Using VHDL"
Class Dates: June 26-30
Time: 8:30 AM to 5:00 PM
Location: Residence Inn, Portland West
Just West of Beaverton, OR
"A Comprehensive Introduction to Top Down Design Using Verilog"
Class Dates: July 17-21
Time: 8:30 AM to 5:00 PM
Location: Qualis Design Corporation
Special room rates are available at The Residence Inn for
Qualis Training -- contact Qualis for more details.
Intended Audience
-----------------
"A Comprehensive Introduction to Top Down Design Using
VHDL (or Verilog)" is intended for hardware and software
engineers and system architects who wish to gain a solid
grounding in, and wish to understand how to use VHDL or
Verilog for system design and simulation. Others who
wish to understand the features and benefits of VHDL and
Verilog will also profit from this course.
"A Comprehensive Introduction to Top Down Design Using Verilog"
-----------------------------------------------------------
"A Comprehensive Introduction to Top Down Design Using
Verilog" is a fast paced, 5-day hands-on, multi-media
course designed not only to teach the entire Verilog
language, but to make class participants immediately
productive in a synthesis and system simulation
environment using state-of-the-art tools.
Students will have access to individual Sun Sparcstations,
the Verilog simulation environment, and the Synopsys DC
Expert synthesis environment for use during the laboratory
sessions. After an introduction to Verilog, the course
deviates from the traditional bottom-up, gates-to-
behavi{*filter*}modeling presentation of course materials and
reverses the flow, teaching top-down design practices,
with early special emphasis on coding for synthesis,
efficient testbench generation and advanced design
verification techniques. These skills are reinforced
throughout the week while teaching Verilog from a top-down
perspective.
About the Verilog Instructor
----------------------------
"A Comprehensive Introduction to Top Down Design Using
Verilog" is taught by Cliff Cummings, Qualis Director of
Training and a Principal Engineer who has completed many
ASIC and FPGA designs and system simulation projects. Mr.
Cummings is capable of answering the very technical
questions asked by experienced design engineers.
Mr. Cummings is a principal member of the IEEE 1364
Verilog Standardization committee and has taught dozens of
Verilog classes and advanced Verilog HDL seminars. He has
also presented eight papers on topics including ASIC test
vector generation, FPGA design methodologies, Verilog
passive device modeling, board test generation techniques,
and inter-tool flow for system simulation. Two of Mr.
Cummings' works were voted Best Paper at the 1993 and 1994
International Cadence Users Conferences.
Mr. Cummings, who holds a BSEE from Brigham Young
University and an MSEE with Computer Science minor from
Oregon State University, is a member of the IEEE and the
Eta Kappa Nu, Tau Beta Pi and Sigma Delta Pi Honor Societies.
Additional Information
----------------------
Course fee includes all training materials and books, daily
continental breakfast, full lunch, afternoon refreshments,
framed course completion certificates and awards.
For more information about Qualis Top-Down courses, including
course description and syllabus, contact us at:
Qualis Design Corporation
15455 NW Greenbrier Parkway
Suite 250
Beaverton, OR 97006
Phone: (503) 531-0377
(please specify which course)
E-Mail Updates
--------------
Information about advanced Top-Down training using Verilog
& VHDL is e-mailed to engineers who may be interested in
current and future Qualis training and seminars including:
Testbenches & Synthesis using Verilog or VHDL, Synthesis
for FPGAs, Advanced HDL project strategies, LM Hardware
Modeling for Verilog or VHDL, Co-simulation using Verilog
& VHDL.
If you would like to be added to our e-mail distribution
list, please send your name and e-mail address to
Qualis also publishes Verilog, VHDL, and 1164-Package
Quick Reference Cards which will soon be available at a
Qualis FTP site where engineers will be encouraged to
freely copy postscript versions of these Cards for
personal and company use. Details will be e-mailed at a
later date.
About Qualis Design Corporation
-------------------------------
Qualis Design Corporation is the leading independent
provider of top-down consulting, design, and training
services. The company provides services to leading-edge
high technology firms worldwide. Qualis HDL Training
Courses are conducted on leading-edge Sun workstations
using the latest EDA vendor tools, and are taught by
engineering professionals with extensive digital design
experience. Engineers who complete the Qualis VHDL &
Verilog Training Courses will be more efficient users of
system simulation tools, will be capable of implementing
advanced simulation environments, and will have the
knowledge to successfully complete complex design
projects. Engineers with previous exposure to VHDL and
Verilog will also benefit from the leading-edge material
presented.
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Copyright (c) 1995 Qualis Design Corporation. All rights reserved.
"DC Expert" is a trademark of Synopsys, Incorporated
"Verilog" is a registered trademark of Cadence Design Systems
Regards - Cliff Cummings
============================================================================
= Cliff Cummings - Director of Training, Principal Engineer
= Verilog/Xilinx/LMC Training, Consulting & Contracting
= Qualis Design Corporation
= 15455 N.W. Greenbrier Parkway Voice: (503) 531-0377
= BEAVERTON OR 97006 FAX: (503) 629-5525
============================================================================
