Variable/Signal assigned by multiple non-blocking assignments 
Author Message
 Variable/Signal assigned by multiple non-blocking assignments

begin

       state_counter   <=  state_counter - 5'd1; /// default

       case  (state)

       IDLE   : if (start)  
                begin
                state_counter   <= 5'd31;  /// change the default
                state               <=  NORMAL
                //~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~/
                end

      NORMAL  :   state   <=  OTHER /// use the default   of
state_counter

      OTHER   :    state <= IDLE /// use the default

     default  :    begin
                   state_counter   <= 5'd31;  /// change the default
                   state  <= IDLE
                   end
     end case
...............

The Modelsim simulator we are using overwrites  the result by the last
assignment. ( Which means that it actually takes the last one)
As a result in the case of "NORMAL"  - > state_counter   <=
state_counter - 5'd1;
and in the case of " IDLE"   - >state_counter   <= 5'd31  although  it
previously gets   state_counter   <=  state_counter - 5'd1;
Can you assure me that Synopsys has the same behavior ???

Thanks
Dror Arad
Intel Haifa
972-4-8656805



Thu, 05 Feb 2004 22:52:27 GMT  
 Variable/Signal assigned by multiple non-blocking assignments

Quote:

> The Modelsim simulator we are using overwrites??the?result?by?the?last
> assignment. ( Which means that it actually takes the last one)
> As a result in the case of "NORMAL"??-?>?state_counter???<=
> state_counter - 5'd1;
> and in the case of " IDLE"???-?>state_counter???<=?5'd31??although??it
> previously gets???state_counter???<=??state_counter?-?5'd1;
> Can you assure me that Synopsys has the same behavior ???

yes it does (though during simulation it will glitch to "state_counter?-?
5'd1" and back to 5'd31 in 0-time which won;t be a problem unless you are
doing something really wierd with it - like using it as a clock)

        Paul



Fri, 06 Feb 2004 05:28:41 GMT  
 Variable/Signal assigned by multiple non-blocking assignments


Quote:

>> The Modelsim simulator we are using overwrites??the?result?by?the?last
>> assignment. ( Which means that it actually takes the last one)
>> As a result in the case of "NORMAL"??-?>?state_counter???<=
>> state_counter - 5'd1;
>> and in the case of " IDLE"???-?>state_counter???<=?5'd31??although??it
>> previously gets???state_counter???<=??state_counter?-?5'd1;
>> Can you assure me that Synopsys has the same behavior ???

>yes it does

agreed

Quote:
>(though during simulation it will glitch to "state_counter?-?
>5'd1" and back to 5'd31 in 0-time which won;t be a problem unless you are
>doing something really wierd with it - like using it as a clock)

not agreed at all - *both* nonblocking assignments execute in the
same simulation cycle, and only the last of them gets implemented, no?

Au contraire, had they been blocking assignments (a Bad Idea) there
would indeed have been a zero-width glitch which could have triggered

--
Jonathan Bromley
DOULOS Ltd.
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Fri, 06 Feb 2004 21:07:00 GMT  
 Variable/Signal assigned by multiple non-blocking assignments

Quote:

>>(though during simulation it will glitch to "state_counter?-
>>5'd1" and back to 5'd31 in 0-time which won;t be a problem unless you are
>>doing something really wierd with it - like using it as a clock)

> not agreed at all - both nonblocking assignments execute in the
> same simulation cycle, and only the last of them gets implemented, no?

> Au contraire, had they been blocking assignments (a Bad Idea) there
> would indeed have been a zero-width glitch which could have triggered


what the LRM sais basicly is that when non-blocking assignements are queued
to be delivered to the same reg at the same time then the order is
undefined EXCEPT in the special (and somewhat common) case where they are
from the same always block in which case they are executed in order.

Now the LRM refers them as seperately queued events - I think that a
simulator 'collapsing' them into single assignment would probably be OK -
but maybe not quite legal - someone might legally expect:

                        a <= 0;
                        a <= 1;
                        a <= 0;

                        ...


                                $display("trigger");

to trigger (personally I think that this ought to be undefined)

                Paul



Sat, 07 Feb 2004 05:11:20 GMT  
 
 [ 4 post ] 

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