SPeeDCHART 
Author Message
 SPeeDCHART

I am evaluating a tool called SPeeDCHART.  It is supposed to allow the
graphical creation of finite state machines and datapaths.  After a
compiling, it is able to generate verilog or vhdl.  I have just looked
at it for a few days and it looks fairly good, although documendation
and tech support isn't very good yet.

I would be interested to know if anyone else has evaluated this product and
what the conclusions were.  Are there other competing products which are
able to generate verilog from a graphical description?

__________________________________________________________________________
James S. H. Cho h: (415) 494-8344 o: 725-3649 o _   _ _  _   _  _   /   _
Center for Integrated Systems, Elec. Eng.    / /_\ /\/\ /_\ /_ /   / \ / \
CIS-038, MC-4070, Stanford, CA 94301     \__/ /  //   / \_  _/ \_//  / \_/



Sun, 26 May 1996 06:15:04 GMT  
 SPeeDCHART
Yes there are.  Look at Design Expressions from Intergraph Electronics.  It generates
both VHDL and Verilog for state charts and datapaths.
Gabe


Tue, 28 May 1996 07:05:51 GMT  
 SPeeDCHART

Quote:

>Yes there are.  Look at Design Expressions from Intergraph Electronics.
It generates
>both VHDL and Verilog for state charts and datapaths.
>Gabe

You can look at ExpressV-HDL from i-Logix too, which seems to do the same
thing as Design
Expression (translation of Statecharts into VHDL and Verilog).
Jerome.


Tue, 28 May 1996 16:29:15 GMT  
 SPeeDCHART

Quote:

>I am evaluating a tool called SPeeDCHART.  It is supposed to allow the
[Stuff deleted]
>what the conclusions were.  Are there other competing products which are
>able to generate verilog from a graphical description?

Yes there are. Try ExpressV-HDL from i-Logix. ExpressV-HDL is a tool
in which the designer graphically create behavioural models. The models
are then compiled and ExpressV-HDL generates Verilog? (or VHDL) code.

Raimo

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Tue, 28 May 1996 20:49:53 GMT  
 
 [ 4 post ] 

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