elaboration error 
Author Message
 elaboration error

Is there a way around the elaboration error:

SPC_Error: Target 'c' is incompatible with assigned value
        in routine rs line * in file 'xx.vhd' (HDL-40)
in the following example:

LIBRARY IEEE;
USE IEEE.std_logic_1164.all;
ENTITY rs IS
  GENERIC (width : integer := 5);
  PORT (
    a : IN  Std_Logic_Vector(width-1 downto 0);
    c : OUT Std_Logic_Vector(width-1 downto 0));
END rs;

ARCHITECTURE abc OF rs IS
FUNCTION ac ( a : Std_Logic_Vector)  
  RETURN Std_Logic_Vector IS
  VARIABLE s : Std_Logic_Vector(a'LENGTH downto 0);
BEGIN
  s:= (others => '0');
  IF (s'LENGTH > a'LENGTH) THEN
    RETURN s;      
  ELSE            
    RETURN s(a'LENGTH-1 downto 0);
  END IF;
END ac;
BEGIN  
  PROCESS (a) BEGIN
    c <= abc(a);                  
  END PROCESS;
END abc;



Mon, 23 Aug 1999 03:00:00 GMT  
 elaboration error

oops wrong news group!



Mon, 23 Aug 1999 03:00:00 GMT  
 
 [ 2 post ] 

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