VLSI Design Verification openings at Ross Technology, AUSTIN, TX 
Author Message
 VLSI Design Verification openings at Ross Technology, AUSTIN, TX

Ross Technology in Austin, Texas is looing for full-time and summer
hires for the following positions:
Required Experience: All levels starting from B.S. EE/CS can apply
Ross Technology is an equal opportunity employer

Random Test Pattern Generation (RTPG)
        - Random Instruction Generation/Automatic Test Generation
        - Assembly code programming
        - Programming/Object-oriented programming
          PERL, C, C++
        - Computer Architecture
        - UNIX/Operating System knowledge
        - GUI programming

Familiar with the following:
        - application instruction set
        - system instruction set
        - speculative execution (reorder buffer)
        - paging
        - cache coherency
        - branch prediction
        - bus interface (prefer P54C/P6 or PPC-60x)
        - multi-processing (locks / arb / sharing)
        - external interrupts
        - floating point

Block-level validation
        - regression testing
        - define validation methodology

Simulation
        - Micro-architectural simulations
        - Setting up simulation environments
        - Gate-level RTL, preferably Verilog, simulation
        - RTL level logic design preferably in Verilog

Familiar with the following:
        - cycle-based simulators
        - model builds

Silicon debug
        - Design for testibility
        - Silicon debug hooks (definition & implementation)
        - Speed paths
        - JTAG / SCAN methodology

Formal verification
        - RTL to GATE
        - Model checking
        - Mathmatical theorem proving
------------------------------------------------------------
Nikhil Dakwala
Lead DFT, Ross Technology
Nations Bank Bldng.
5316 HWY 290 West, Austin, Tx 78735
512 436 2701 (fax)



Sun, 26 Sep 1999 03:00:00 GMT  
 
 [ 1 post ] 

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