Recent article on design verification 
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 Recent article on design verification


> Tonight I was thumbing through an article on design verification
> in "Integrated System Design" by Saunders and Trivedi and have
> a few comments.

> 1) First of all, this is the first time I've heard a DV environment
> referred to as a "testbench". I've been doing DV for 15 years,
> focussing exclusively on DV for the past 10. I usually call it
> an design verificaton environment or a test suite for short.

>I have called it a "testbench" for some time.  I think the VHDL
>community has adopted this term too.

I've seen the phrase "testbench" used in the Verilog based design community
since 88-89 and the VHDL community has used it at least since 1992 (mind
you, I'm not quoting some "official" history -- I'm just remembering off
the top of my head as an ASIC design engineer....)


> 2) They "recommend highly" that the "testbench" be written in the
> same language as the "DUT". Whoa. Has anyone ever tried to write
> an expert system in verilog? Depending on the circuit complexity,
> that's exactly what you'll need if you have a fair number of
> stimulus constraints. Verilog is not a high level language. It's
> perhaps a 2.5 generation language, somewhere between assembly and C.

>Certianly there are things that are hard to write in Verilog.  But
>for those cases where the language is usable, it really helps
>productivity to use one language for both the testbench and the DUT.
>Otherwise the designer has to switch back and forth.

John, Don,

I think you're both missing why Verilog had a PLI installed in the first
place -- so engineers could talk directly to & from the Verilog simulation
from another higher level language (most typically C but I see no reason
why a few of the other Computer Science-type languages couldn't take
advantage of the PLI if so inclined.)

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Sun, 28 Sep 1997 03:00:00 GMT  
 [ 1 post ] 

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