Recent article on design verification 
Author Message
 Recent article on design verification

Quote:

> Tonight I was thumbing through an article on design verification
> in "Integrated System Design" by Saunders and Trivedi and have
> a few comments.

> 1) First of all, this is the first time I've heard a DV environment
> referred to as a "testbench". I've been doing DV for 15 years,
> focussing exclusively on DV for the past 10. I usually call it
> an design verificaton environment or a test suite for short.

>I have called it a "testbench" for some time.  I think the VHDL
>community has adopted this term too.

I've seen the phrase "testbench" used in the Verilog based design community
since 88-89 and the VHDL community has used it at least since 1992 (mind
you, I'm not quoting some "official" history -- I'm just remembering off
the top of my head as an ASIC design engineer....)

Quote:

> 2) They "recommend highly" that the "testbench" be written in the
> same language as the "DUT". Whoa. Has anyone ever tried to write
> an expert system in verilog? Depending on the circuit complexity,
> that's exactly what you'll need if you have a fair number of
> stimulus constraints. Verilog is not a high level language. It's
> perhaps a 2.5 generation language, somewhere between assembly and C.

>Certianly there are things that are hard to write in Verilog.  But
>for those cases where the language is usable, it really helps
>productivity to use one language for both the testbench and the DUT.
>Otherwise the designer has to switch back and forth.

John, Don,

I think you're both missing why Verilog had a PLI installed in the first
place -- so engineers could talk directly to & from the Verilog simulation
from another higher level language (most typically C but I see no reason
why a few of the other Computer Science-type languages couldn't take
advantage of the PLI if so inclined.)

                           - John Cooley
                             Part Time EDA Consumer Advocate
                             Full Time ASIC, FPGA & EDA Design Consultant

===========================================================================
 Trapped trying to figure out a Synopsys bug?  Want to hear how 3271 other
 users dealt with it ?  Then join the E-Mail Synopsys Users Group (ESNUG)!


     /o o\  /  it's a FEATURE!"                 (508) 429-4357
    (  >  )
     \ - /     - John Cooley, EDA & ASIC Design Consultant in Synopsys,
     _] [_         Verilog, VHDL and numerous Design Methodologies.

     Holliston Poor Farm, P.O. Box 6222, Holliston, MA  01746-6222
   Legal Disclaimer: "As always, anything said here is only opinion."



Sun, 28 Sep 1997 03:00:00 GMT  
 
 [ 1 post ] 

 Relevant Pages 

1. Recent article on design verification

2. Recent article on design verification

3. Recent articles on Python

4. Recent article in UniNews

5. Recent CACM "viewpoint" article

6. recent article on Fortran and C

7. Question regarding a recent article on informit.com

8. Yourdan's recent article on SM

9. Postdoc vacancy for multi-rate / protocol IC-design verification

10. B02 LOGIC DESIGN AND VERIFICATION V5.0 new !

11. Transition from pre-design to pose verification

12. ASIC Design / Verification Engineers looking for job

 

 
Powered by phpBB® Forum Software