Getting started with SystemC 
Author Message
 Getting started with SystemC

Now that you know VHDL and or Verilog, are you interested in finding
out what SystemC is all about? Want to get "primed" with SystemC?

The book "A SystemC Primer" can get you on the right path ....

ISBN: 0-9650391-8-8
Author: J. Bhasker
Publisher: Star Galaxy Publishing
Price: $69.95

Its now available at http://www.*-*-*.com/ or can be ordered through
any bookstore.

- bhasker



Thu, 20 Jan 2005 23:48:42 GMT  
 Getting started with SystemC
What advantages would system c offer over vhdl and verilog?
Shibu
Quote:

> Now that you know VHDL and or Verilog, are you interested in finding
> out what SystemC is all about? Want to get "primed" with SystemC?

> The book "A SystemC Primer" can get you on the right path ....

> ISBN: 0-9650391-8-8
> Author: J. Bhasker
> Publisher: Star Galaxy Publishing
> Price: $69.95

> Its now available at http://www.amazon.com or can be ordered through
> any bookstore.

> - bhasker



Fri, 21 Jan 2005 09:39:20 GMT  
 Getting started with SystemC
Quote:

> What advantages would system c offer over vhdl and verilog?
> Shibu

SystemC is one possible solution to very serious problem:
how to describe contents of most advanced ASICs and FPGAs that may
contain both low level primitives (gates, flip-flops) and and complete
processors?
Verilog (even 2001 version) is not suitable solution here (I don't
consider using PLI as manageable solution) due to weak support of
higher abstraction levels. VHDL is a little bit better, but not
perfect.
SystemC is using object oriented programming concept of classes,
implemented in C++. It defines parent classes describing ports,
modules, signals, processes, etc. from which your code can build
hardware and software descriptions using inheritance mechanizm.
To simulate your design you can use standard C++ streams for console
output or library methods for creation of VCD files that can be viewed
in third party software. Compiled SystemC design is an executable that
you can run from your system prompt.
SystemC advantages:
- very high simulation speed
- one language environment for mixed hardware/software design
- high level of abstraction available - suitable for system
  descriptions
Disadvantages:
- requires some familiarity vith C++ (good for software engineers,
  hardware engineers seem to be more familiar with plain C and
  similar languages)
- weak support from other tools (design entry, synthesis, etc.)
- uncertain future (some big companies smelling even bigger money
  are trying to push alternative solutions, e.g. System Verilog)
Generally speaking:
- if you are doing HUGE designs for ASICs and largest FPGAs
  (or design systems on silicon) you may benefit from SystemC
- if you are doing small/medium size designs and already know
  Verilog/VHDL - stick to them for now and wait till situation
  clarifies
- if you want to be up-to-date with new technologies, visit
   http://www.SystemC.org
  to check if you like the idea, then decide if you want to invest
  in books.

Jerry



Fri, 21 Jan 2005 23:41:51 GMT  
 Getting started with SystemC

Quote:

> Thanks for your thoughts but I'll heartily disagree...



> > > The big question is why would you want to model pull-ups or
> > > transmission gates when you are trying to simulate an entire 50
> > > Million gate system (except if you are perhaps Intel).
> > > If you are
> > > doing this I'd question your methodology...

> > Using pull-ups or transmission gates is design, not methodology...

> If you are designing or even doing system verification of a big SoC
> (vs. doing final tuning of design and signoff verification) at the
> pullup and transmission gate level, then you are nowhere near as
> productive as folks with a high level design methodology.

I get your point, but if you have (for example) an I2C in your design,
then you must model a pull-up with a real delay or you cannot sign-off
on that simulation.

Your other points are also interesting. I suppose that in reality each
customer evaluating a SystemC tool will do its own speed checks, becuase
you can never believe anything a vendor tells you (except Cadence, of
course :-)

Quote:
> As for testbenches, I understand from your alma mater (Cadence) that
> Cadence is adding the testbench technology to SystemC including the
> ability to reuse the same system-level testbenches at the gate level
> through an HDL link used in TestBuilder today.

> Am I wrong ?? Is the design verication group fibbing to me... Ijust
> saw this paper at DAC where the Cadence guy was giving them out.

I haven't previously been following Cadence's developments in the
SystemC area with much detail: just seeing the headlines on press
releases. I'm sure that Cadence are doing what you said... it just
worries me that plugging a cycle-accuarte simulation into a
non-cycle-accurate testbench may lose something that a totally
cycle-accurate sim might have. But maybe this has been thought of by our
marvellous R&D team.

Quote:
> My experience with processor design in the 80's tells me that all
> processors start out as an instruction set simulator in C/C++ (or
> maybe in ARM7 case Pascal !) so people can analyze typical code
> streams, look for bottlenecks and make decisions about the
> architecture, cache sizes, etc.  This architectural ISS is then used
> as the reference model for the implementation.  Look at any company
> doing processor design.  Ask ARM !

That's true. However, I'm not sure that that original ISS
experimentation platform would be used as a PLI-type plug-in. Too many
implementation changes might occur. OK, I suppose that's a methodology
and revision control issue.

Quote:
> Semaless
> > was invented to run CPUs faster with instruction simulators instead of
> > HDL, not because the CPUs were only available as C...

> Not just because the C++ ISS runs faster than HDL, but also because
> many STAR IP suppliers won't even give up "Implementation HDL", or
> charge much more for it.

But you get C models for PLI-add ins to normal simulators which don't
offer the speed advantages that Seamless has. In fact, due to the
inefficiencies of PLI-1.0 then it can even be slower than RTL...!

Quote:
> > AFAIK, ncsim will be the first integrated SystemC/VHDL/Verilog one...
> > please correct me if I'm wrong.

> CoWare and Synopsys have both offered to sell me mixed SystemC/HDL
> simulation now.

I meant that ncsim was the first with VHDL too... Synopsys' VHDL support
is a bit of a bodge: I don't know how CoWare do VHDL (if they do it at
all).

Thanks for your debunking of some of my incorrect perceptions. I'm just
off to re-read my copy of Stroustoup to make sure I don't get swept away
by a tidal wave of softies designing hardware :-)

--

  L_   _|   Senior Design Engineer
    | |     Tality, Alba Campus, Livingston EH54 7HH, Scotland
    ! |     Phone: +44 1506 595360        Fax: +44 1506 595959

T A L I T Y                http://www.tality.com



Fri, 28 Jan 2005 17:12:18 GMT  
 Getting started with SystemC

Quote:


> I get your point, but if you have (for example) an I2C in your design,
> then you must model a pull-up with a real delay or you cannot sign-off
> on that simulation.

You are indeed right - though we use SystemC, we still use a little
Verilog, plus a lot of static timing analysis for signoff.

Quote:

> Your other points are also interesting. I suppose that in reality each
> customer evaluating a SystemC tool will do its own speed checks, becuase
> you can never believe anything a vendor tells you (except Cadence, of
> course :-)

We haven't tried what the Fujitsu guys did, but my experience with
tools like Seamless tell me that mixed HW/SW simulation can be made a
lot faster if you don't have the mess of overhead of PLI's plus
executing code on a virtual processor / ISS (vs. running the code
directly)

Quote:

> I haven't previously been following Cadence's developments in the
> SystemC area with much detail: just seeing the headlines on press
> releases. I'm sure that Cadence are doing what you said... it just
> worries me that plugging a cycle-accuarte simulation into a
> non-cycle-accurate testbench may lose something that a totally
> cycle-accurate sim might have. But maybe this has been thought of by our
> marvellous R&D team.

The guys at Cadence are bringing some truly neat stuff to SystemC by
improving on TestBuilder (by integrating its concepts into SystemC
environment), allowing us to think in terms of transactions for
verification and handling the non-cycle accurate / cycle accurate
challenge in the process (at least on paper, I haven't seen the code
yet !)

Quote:
> That's true. However, I'm not sure that that original ISS
> experimentation platform would be used as a PLI-type plug-in. Too many
> implementation changes might occur. OK, I suppose that's a methodology
> and revision control issue.

In many cases, original ISS is morphed into early sofware validation
model, then into cycle accurate (or cycle-callable as ARM prefers to
call them) model for verification.

Quote:
> > Not just because the C++ ISS runs faster than HDL, but also because
> > many STAR IP suppliers won't even give up "Implementation HDL", or
> > charge much more for it.

> But you get C models for PLI-add ins to normal simulators which don't
> offer the speed advantages that Seamless has. In fact, due to the
> inefficiencies of PLI-1.0 then it can even be slower than RTL...!

My take on Seamless is that it gets rid of most of the PLI gleet and
overhead, but still doesn't offer the benefit of software talking
directly to "bus" without ISS.. I'm still doing experiments, but I
expect result similar to the ST guy's where verification with software
runs 40-50x, tuned RTL/ISS environment like Seamless. Foil 10 gives a
pretty good comparison
http://www-ti.informatik.uni-tuebingen.de/~systemc/Documents/Presenta...

Quote:
> > CoWare and Synopsys have both offered to sell me mixed SystemC/HDL
> > simulation now.

> I meant that ncsim was the first with VHDL too... Synopsys' VHDL support
> is a bit of a bodge: I don't know how CoWare do VHDL (if they do it at
> all).

I'm not doing VHDL and won't have to worry about incorporating legacy
Verilog for another 6 months.  Maybe Cadence product will be shipping
then and I'll have three to play with and decide !

Quote:

> Thanks for your debunking of some of my incorrect perceptions. I'm just
> off to re-read my copy of Stroustoup to make sure I don't get swept away
> by a tidal wave of softies designing hardware :-)

My problem is that there are aready a bunch of "softies" in our design
group and we're suppose to play nicely with them - They want a HW
model to start running software (OS plus aplication layer) on 11
months before we start tapeout... Help !

Jeanan



Sun, 30 Jan 2005 13:02:52 GMT  
 
 [ 5 post ] 

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