Parameterized functions? 
Author Message
 Parameterized functions?

Sorry to say, no.  Parameterization in verilog is limited to
modules.  Functions must be explicitly fixed to bitwidths.  Of
course, functions in a module may use the modules parameters.

Quote:

> New to Verilog..
> I'm trying to model parameterized functions.  How would one
> do such a thing thru an example?  For instance, I want to
> implement something similar to below VHDL function:

>  FUNCTION something (l,r:STD_LOGIC_VECTOR) RETURN STD_LOGIC_VECTOR IS...

> The above function operates on any size input and would
> return any size output (dependent on input size).

> Is it possible within Verilog to do the same?

> Thanks,
> Mike Sullivan


--
Robert Hoffman
Consultant, System & ASIC Design Engineer

.. Work  : 408-249-4847


Sat, 21 Aug 1999 03:00:00 GMT  
 
 [ 1 post ] 

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