ifdef statement 
Author Message
 ifdef statement

Hi everyone,
I was looking at some old verilog code and it goes like this

'define ABC
reg test;
initial
begin
'ifdef ABC
memory_write;
'endif
test = 0;
$finish
end

My question is:
What does the statement memory_write do? I have checked in other parts
of the code and it is not a module or a function. I would assume it is
a function call to do something !!

Thanks in advance,
(Searching for knowledge)



Wed, 20 Oct 2004 08:59:29 GMT  
 ifdef statement

Quote:
> Hi everyone,
> I was looking at some old verilog code and it goes like this

> 'define ABC
> reg test;
> initial
> begin
> 'ifdef ABC
> memory_write;
> 'endif
> test = 0;
> $finish
> end

> My question is:
> What does the statement memory_write do? I have checked in other parts
> of the code and it is not a module or a function. I would assume it is
> a function call to do something !!

Hope you understood the ifdef concept. And i think the code whih you
have seen, is just to explain about the ifdef concept..

and there could be a task 'memory_write'.

- Show quoted text -

Quote:
> Thanks in advance,
> (Searching for knowledge)



Wed, 20 Oct 2004 17:33:59 GMT  
 ifdef statement

Quote:
> 'define ABC
> reg test;
> initial
> begin
> 'ifdef ABC
> memory_write;
> 'endif
> test = 0;
> $finish
> end

> My question is:
> What does the statement memory_write do? I have checked in other parts
> of the code and it is not a module or a function. I would assume it is
> a function call to do something !!

With that syntax, it must be a call to a Verilog task defined in this
module.  The `ifdef simply determines whether the task will get called
by conditionally controlling whether that source line gets compiled or
not.  If ABC has been defined (as it has in your example), and memory_write
is not declared, then this code is erroneous (or at least incomplete).


Thu, 21 Oct 2004 04:26:44 GMT  
 ifdef statement
Thank you very much for your help people.

It was indeed a task and i was missing some files. I was pretty sure
too of it being a task but since i could not find a file anywhere i
thought maybe there was something else in verilog i did not know of.

Thanks again.
(Searching for knowledge)

Quote:


> > 'define ABC
> > reg test;
> > initial
> > begin
> > 'ifdef ABC
> > memory_write;
> > 'endif
> > test = 0;
> > $finish
> > end

> > My question is:
> > What does the statement memory_write do? I have checked in other parts
> > of the code and it is not a module or a function. I would assume it is
> > a function call to do something !!

> With that syntax, it must be a call to a Verilog task defined in this
> module.  The `ifdef simply determines whether the task will get called
> by conditionally controlling whether that source line gets compiled or
> not.  If ABC has been defined (as it has in your example), and memory_write
> is not declared, then this code is erroneous (or at least incomplete).



Sat, 23 Oct 2004 07:50:04 GMT  
 ifdef statement
Hi all,

We normally using `ifdef for conditional compilation. Is that is
synthesizable or not? shall we use it in the implementation phase?

If not, can anyone suggess any idea to support `ifdef kind of thing in
synthesize...

Actually i want to parametirise my design with `ifdef... thats why...

thanks in advance..

Best regards,
Muthu



Sat, 23 Oct 2004 21:24:51 GMT  
 ifdef statement


Quote:
>We normally using `ifdef for conditional compilation. Is that is
>synthesizable or not? shall we use it in the implementation phase?

Yes, `ifdef is OK for synthesis.  After all, it is simply the
conditional removal of some source text from your code.

Synopsys DC does not accept `ifdef by default.  To use `ifdef,
you need to set the compiler variable hdlin_enable_vpp to "true".
--
Jonathan Bromley
DOULOS Ltd.
Church Hatch, 22 Market Place, Ringwood, Hampshire BH24 1AW, United Kingdom

Fax: +44 1425 471573                             Web: http://www.doulos.com

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This e-mail and any  attachments are  confidential and Doulos Ltd. reserves
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are not the views of Doulos Ltd., unless specifically stated.



Sat, 23 Oct 2004 21:37:41 GMT  
 ifdef statement
There must be a task, otherwise, the code will not pass compilation.



Quote:
> Hi everyone,
> I was looking at some old verilog code and it goes like this

> 'define ABC
> reg test;
> initial
> begin
> 'ifdef ABC
> memory_write;
> 'endif
> test = 0;
> $finish
> end

> My question is:
> What does the statement memory_write do? I have checked in other parts
> of the code and it is not a module or a function. I would assume it is
> a function call to do something !!

> Thanks in advance,
> (Searching for knowledge)



Mon, 25 Oct 2004 23:27:36 GMT  
 ifdef statement

Quote:



> >We normally using `ifdef for conditional compilation. Is that is
> >synthesizable or not? shall we use it in the implementation phase?

> Yes, `ifdef is OK for synthesis.  After all, it is simply the
> conditional removal of some source text from your code.

> Synopsys DC does not accept `ifdef by default.  To use `ifdef,
> you need to set the compiler variable hdlin_enable_vpp to "true".
> --
> Jonathan Bromley
> DOULOS Ltd.
> Church Hatch, 22 Market Place, Ringwood, Hampshire BH24 1AW, United Kingdom

> Fax: +44 1425 471573                             Web: http://www.doulos.com

>                    **********************************
>                    **  Developing design know-how  **
>                    **********************************

> This e-mail and any  attachments are  confidential and Doulos Ltd. reserves
> all rights of privilege in  respect thereof. It is intended for the  use of
> the addressee only. If you are not the intended  recipient please delete it
> from  your  system, any  use, disclosure, or copying  of this  document  is
> unauthorised. The contents of this message may contain personal views which
> are not the views of Doulos Ltd., unless specifically stated.

Hi,

Yeah as you said, it is working fine.

and Is any one tried this `ifdef synthesise using "Synplify_pro". What
option has to be set to make it synthesizable in "Synplify_pro"....

Thanks in advance

Best regards,
Muthu



Tue, 02 Nov 2004 22:03:55 GMT  
 
 [ 8 post ] 

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