Newbie Help: clock with phase delay 
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 Newbie Help: clock with phase delay

I am a newbie to this interesting verilog language,
and I am having with implementing a phase delay to a
clock source... for a class assignment.  Please give
some hints or ideal on how to implement this.

I have

module clk(clock);
output clock;
reg clock;
parameter period = 100;
parameter duty = 50;

initial clock = 1;
always fork
        #(duty*period/100) clock = ~clock;
        #period clock = ~clock;
        join
endmodule

How do I change this to have the clock shifted by some
n time?

Thanks in advace



Sat, 03 Feb 2001 03:00:00 GMT  
 
 [ 1 post ] 

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