Do gray code counters comsume less power 
Author Message
 Do gray code counters comsume less power

As gray code counter have only one bit changing at any time do they
consume less power.


Thu, 18 Dec 2003 21:54:18 GMT  
 Do gray code counters comsume less power
My feel is: generally no.

If you're driving very heavy capacitive loading so that 90% of your
power is in your line drivers, gray can be the way to go.  If you're
trying to cut down on logic power, binary can give you comparable
results to gray.

How do you implement a gray counter?  You get about half the transitions
of a binary counter, half the lines driven by the counter output have to
be charged/discharged.

From an FPGA perspective if you're dealing with small counters (4 bits
or fewer) you get the savings, but how much power is used by this
counter?  In a large design, the difference is in the noise level.

If you want to implement a large counter, the logic to generate the gray
counter isn't natively supported in FPGAs.  If you use ASICs you have
the opportinity to apply your own logic but you might lose out here,
too.  You need to generate an enable from LSBs up and a parity (for
direction) from the MSBs down.

While binary counters have a toggle that only fully enables when the
toggle is to occur (like the enables generated by the gray counter
LSBs), the gray counter polarity signal at any one particular bit will
toggle every time an MSB changes.  So...

If you're dealing with an ASIC you have the tradeoff of the binary
2^(n+1)-2 register toggles plus 2^(n+1)-2 toggle-enable drives versus
the gray 2^n register toggles, 2^n toggle-enable drives *plus* a rapidly
increasing number of parity signals ( 2 + (2+2) + (2+2+4) + (2+2+4+8) +
(2+2+4+8+16)+...).  The parity signals could be gated by the enable for
each stage so that only the LSB polarity required in the gating is
always enabled, but this polarity changes every cycle.  You might as
well have 2^(n+1) transitions to account for that polarity transitioning
every cycle.

Sound ugly?  My first gray counter wasn't a true gray - I used a
"polarity" register below the LSbit to drive the enable so I got my 2^n
register transitions plus my 2^n polarity transitions.  This is no
savings over binary.  If my polarity register ever missed a toggle, I'd
be counting the wrong direction.

If I used the nice large gray counter technique mentioned recently by
Peter Alfke over on comp.arch.fpga, I'd use an n-bit binary counter
*plus* an additional n-1 XOR gates.  This just adds power.

So, if you have the heavy capacitive drive - go for it!  Otherwise, if
you don't need gray you're probably much better off in the binary world.

- John

Quote:

> As gray code counter have only one bit changing at any time do they
> consume less power.



Fri, 19 Dec 2003 03:38:33 GMT  
 Do gray code counters comsume less power
Depending on you environment and target, you might find yourself better off
with one hot or another one bit per state style, which ensures two edges per
state transition and narrower logic equations for state transitions.  You
have to trade that against extra flops / loads on the clock trunk.  In FPGA
land where the clock tree is given (basically), it seems an easy trade
assuming you aren't against a capacity issue.  Then again if you are talking
about gray code counters, I would guess you are targeting an ASIC.


Quote:
> As gray code counter have only one bit changing at any time do they
> consume less power.



Sat, 20 Dec 2003 21:26:06 GMT  
 Do gray code counters comsume less power
You can get a reduced number of terms and number over a 1 hot machine by using a
shift register state machine.  In these, the states are represented by turning
on another bit without turning any off.  The whole register is cleared at once
by the terminal states using a common reset.  For example:

s0 = "0000"
s1= "1000"
s2="1100"
s3="1110"
s4="1111"

It is a bit harder to synthesize or even design than other styles, but it does
give you the utmost in performance in larger state machines.  I used to use this
alot in the older devices such as the XC3000 series.  Not nearly as much now,
partly because of the type designs I am doing don't use big state machines, and
partly because the speeds of modern devices has gone quite far from the "good
old days"

Quote:

> Depending on you environment and target, you might find yourself better off
> with one hot or another one bit per state style, which ensures two edges per
> state transition and narrower logic equations for state transitions.  You
> have to trade that against extra flops / loads on the clock trunk.  In FPGA
> land where the clock tree is given (basically), it seems an easy trade
> assuming you aren't against a capacity issue.  Then again if you are talking
> about gray code counters, I would guess you are targeting an ASIC.



> > As gray code counter have only one bit changing at any time do they
> > consume less power.

--
-Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930     Fax 401/884-7950

http://www.andraka.com


Sun, 21 Dec 2003 03:51:36 GMT  
 Do gray code counters comsume less power
Ray,
This is a good comment on how some ideas re-surface.  I believe the
technique was mentioned in one of Flores's books on computer architecture.
Can't recall the title.  This is a simple and elegant solution, in my
opinion.

While on state-machines... What is your opinion on graphical entry tools for
state-machines?  I think one benefit is documenting the state diagram flow
(ASM).  What do you think?

Thanks.

Jim

Quote:
> You can get a reduced number of terms and number over a 1 hot machine by
using a
> shift register state machine.  In these, the states are represented by
turning
> on another bit without turning any off.  The whole register is cleared at
once
> by the terminal states using a common reset.  For example:

> s0 = "0000"
> s1= "1000"
> s2="1100"
> s3="1110"
> s4="1111"

> It is a bit harder to synthesize or even design than other styles, but it
does
> give you the utmost in performance in larger state machines.  I used to
use this
> alot in the older devices such as the XC3000 series.  Not nearly as much
now,
> partly because of the type designs I am doing don't use big state
machines, and
> partly because the speeds of modern devices has gone quite far from the
"good
> old days"


> > Depending on you environment and target, you might find yourself better
off
> > with one hot or another one bit per state style, which ensures two edges
per
> > state transition and narrower logic equations for state transitions.
You
> > have to trade that against extra flops / loads on the clock trunk.  In
FPGA
> > land where the clock tree is given (basically), it seems an easy trade
> > assuming you aren't against a capacity issue.  Then again if you are
talking
> > about gray code counters, I would guess you are targeting an ASIC.



> > > As gray code counter have only one bit changing at any time do they
> > > consume less power.

> --
> -Ray Andraka, P.E.
> President, the Andraka Consulting Group, Inc.
> 401/884-7930     Fax 401/884-7950

> http://www.andraka.com



Sun, 21 Dec 2003 11:15:52 GMT  
 Do gray code counters comsume less power
I've got mixed feelings.  One can make a state machine readable in various entry
styles (one hots, for instance can be made to look like a flow diagram in a
schematic by putting the appropriate wrappers on them, case statements in VHDL
are also quite readable).  The graphical entry tools abstract the state machine
a little further than I am generally comfortable with for high
performance/density stuff, and require you to learn, maintain and archive yet
another tool.  When designs are being done for customers who may not have the
tools, I try to keep the number of different tools needed to maintain the design
to a minimum.  On the other hand, it does make it much easier to follow someone
else's stuff.

Quote:

> Ray,
> This is a good comment on how some ideas re-surface.  I believe the
> technique was mentioned in one of Flores's books on computer architecture.
> Can't recall the title.  This is a simple and elegant solution, in my
> opinion.

> While on state-machines... What is your opinion on graphical entry tools for
> state-machines?  I think one benefit is documenting the state diagram flow
> (ASM).  What do you think?

> Thanks.

> Jim


> > You can get a reduced number of terms and number over a 1 hot machine by
> using a
> > shift register state machine.  In these, the states are represented by
> turning
> > on another bit without turning any off.  The whole register is cleared at
> once
> > by the terminal states using a common reset.  For example:

> > s0 = "0000"
> > s1= "1000"
> > s2="1100"
> > s3="1110"
> > s4="1111"

> > It is a bit harder to synthesize or even design than other styles, but it
> does
> > give you the utmost in performance in larger state machines.  I used to
> use this
> > alot in the older devices such as the XC3000 series.  Not nearly as much
> now,
> > partly because of the type designs I am doing don't use big state
> machines, and
> > partly because the speeds of modern devices has gone quite far from the
> "good
> > old days"


> > > Depending on you environment and target, you might find yourself better
> off
> > > with one hot or another one bit per state style, which ensures two edges
> per
> > > state transition and narrower logic equations for state transitions.
> You
> > > have to trade that against extra flops / loads on the clock trunk.  In
> FPGA
> > > land where the clock tree is given (basically), it seems an easy trade
> > > assuming you aren't against a capacity issue.  Then again if you are
> talking
> > > about gray code counters, I would guess you are targeting an ASIC.



> > > > As gray code counter have only one bit changing at any time do they
> > > > consume less power.

> > --
> > -Ray Andraka, P.E.
> > President, the Andraka Consulting Group, Inc.
> > 401/884-7930     Fax 401/884-7950

> > http://www.andraka.com

--
-Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930     Fax 401/884-7950

http://www.andraka.com


Sun, 21 Dec 2003 13:15:16 GMT  
 Do gray code counters comsume less power
I also used similar encoding once to pretty good effect, makes generating
timing for bus interfaces quite nice, heard it referred to as a Johnson
counter.  However, you have to know your design (aren't any optimization
techniques dependent on this simple statement).  In complex SMs where the
states don't move very linearly very, this technique isn't near as
effective.  However quite a nice arrow to have in your quiver of tricks if
the target is right.


Quote:
> You can get a reduced number of terms and number over a 1 hot machine by
using a
> shift register state machine.  In these, the states are represented by
turning
> on another bit without turning any off.  The whole register is cleared at
once
> by the terminal states using a common reset.  For example:

> s0 = "0000"
> s1= "1000"
> s2="1100"
> s3="1110"
> s4="1111"

> It is a bit harder to synthesize or even design than other styles, but it
does
> give you the utmost in performance in larger state machines.  I used to
use this
> alot in the older devices such as the XC3000 series.  Not nearly as much
now,
> partly because of the type designs I am doing don't use big state
machines, and
> partly because the speeds of modern devices has gone quite far from the
"good
> old days"


> > Depending on you environment and target, you might find yourself better
off
> > with one hot or another one bit per state style, which ensures two edges
per
> > state transition and narrower logic equations for state transitions.
You
> > have to trade that against extra flops / loads on the clock trunk.  In
FPGA
> > land where the clock tree is given (basically), it seems an easy trade
> > assuming you aren't against a capacity issue.  Then again if you are
talking
> > about gray code counters, I would guess you are targeting an ASIC.



> > > As gray code counter have only one bit changing at any time do they
> > > consume less power.

> --
> -Ray Andraka, P.E.
> President, the Andraka Consulting Group, Inc.
> 401/884-7930     Fax 401/884-7950

> http://www.andraka.com



Tue, 23 Dec 2003 02:58:32 GMT  
 
 [ 7 post ] 

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