Verilog / Synopsys design position 
Author Message
 Verilog / Synopsys design position

GME Designs, Inc is looking for engineers..

About the company:

GME Designs is a small, but very prolific ASIC design house in Calabasas,
(So. California). We have performed over 100 successful ASIC designs since
1987. We are expanding, and must hire at least one more engineer.

We are a Verilog / VHDL / Synopsys house primarily, and have expertise in
SCSI, disk, tape, error correction, DSP systems, network interfaces and
many other areas.

We are looking for a keen engineer, with a flexible approach to design
methodology, and the ability to work in a small company. New graduate or
experienced in other CAE systems is OK, and Verilog or Synopsys experience
a definite plus.

The successful applicant will receive hands on training (as required),
which will
enable him/her to become an expert ASIC designer.


message, or to the aol account. If fax is the only method available, fax
to (818) 880 5193.



Sun, 14 Dec 1997 03:00:00 GMT  
 
 [ 1 post ] 

 Relevant Pages 

1. Verilog & Synopsys Design Compiler warning - ELAB92

2. Synopsys ERROR on this Verilog design

3. JOB OPENINGS: ASIC Design, Datacom, VHDL, Verilog, Synopsys, Synthesis

4. JOB OPENINGS: ASIC Design, Datacom, VHDL, Verilog, Synopsys, Synthesis

5. *** Job: Design VHDL/Verilog/Synthesis Design

6. *** Job: Design VHDL/Verilog/Synthesis Design

7. COURSES: High Level Design Using Verilog, Advanced Techniques Using Verilog, Portland, OR

8. COURSES: High Level Design Using Verilog, Advanced Techniques Using Verilog, Portland, OR

9. COURSES: High Level Design Using Verilog, Advanced Techniques Using Verilog, Portland, OR

10. COURSES: High Level Design Using Verilog, Advanced Techniques Using Verilog, Portland, OR

11. COURSES: High Level Design Using Verilog, Advanced Techniques Using Verilog, Portland, OR

12. COURSES: High Level Design Using Verilog, Advanced Techniques Using Verilog, Portland, OR

 

 
Powered by phpBB® Forum Software