how to create regular structures in verilog 
Author Message
 how to create regular structures in verilog


I tried posting this query sometime back, but seems there was an
error somewhere. So, here it goes again :

How does one go about creating a structural array of some module ?

For example, consider a two dimensional memory array that instantiates
the data-cell "data_cell" p_rows x p_bits number of times. i.e. p_rows
each consisting of an array of size p_bits.


module array ( out_arr, in_arr, sel_arr );
parameter p_rows = 4,
          p_bits = 2;

output [p_bits-1:0] out_arr;
input  [p_bits-1:0] in_arr;
input  [p_rows-1:0] sel_arr;

  row #(p_rows) UR[p_rows-1:0] (out_arr,in_arr,sel_arr);


module row ( out_row, in_row, sel_row );
parameter Dbits = 2;

input  [Dbits-1:0] out_row;
output [Dbits-1:0] in_row;
input sel_row;

data_cell UB[Dbits-1:0] (out_row, in_row, sel_row );



This does not work with Verilo- XL, since the row decl. in
module array has signals which do not have the same size as

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Sun, 03 Feb 2002 03:00:00 GMT  
 [ 1 post ] 

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