Prioritizing transitions in UDPs 
Author Message
 Prioritizing transitions in UDPs

Hi there,
I would like to know if there is a simple mechanism for prioritizing
transitions when two or more inputs change simultaneously.

(The UDP definition does not allow for multiple edges in the same
UDP line. But real world inputs or simulation inputs occur in undefined
unpredictable order)

If prioritization is not done, this leads to race conditions and/or
unpredictable results depending on the implementation of the simulator.


Regards,
Shankar Hemmady



Wed, 01 Jan 1997 00:24:22 GMT  
 Prioritizing transitions in UDPs

Quote:

>Subject: Prioritizing transitions in UDPs
>I would like to know if there is a simple mechanism for prioritizing
>transitions when two or more inputs change simultaneously.

>(The UDP definition does not allow for multiple edges in the same
>UDP line. But real world inputs or simulation inputs occur in undefined
>unpredictable order)

>If prioritization is not done, this leads to race conditions and/or
>unpredictable results depending on the implementation of the simulator.

To the best of my knowledge there is nothing in the UDP definition that allows
prioritizing one transition over another. The two transitions will be in two
different entries of the table. (precisely to avoid dealing with races.)

Note that this must not be considered an inadequacy or flaw in  the language.
This situation has been specifically avoided since in real  life, this  must
not occur and simultaneous transitions cannot occur.

Also, it all depends heavily on what the simulator thinks rather than what the
definition of the table says. If the simulator simply decides to match the
first table entry amongst two competing ones then by default the first transition
entry gets priority. But that would be sort of not-right.

But Verilog-XL does not do this. It performs UDP evaluation multiple times. Here
is what the manual says

"When multiple UDP inputs change at the same simulation time, the UDP will be
evaluated multiple times, once per input value change. This situation cannot be
detected by any form of table entry. ... (showing an example) If the clock
input transition is processed first, then next state will be 0.If the data
input transition is processed first, then next state will be 1.
If its current state is 0 and clock and data inputs make transitions from 0 to 1
at the same time, then the state of the output at the next simulation time is
UNPREDICTABLE (my emphasis) because it cannot be predicted which of these
transitions is processed first..

.....

event-driven simulation is subject to idiosyncratic dependence on the order in
which events are processed."

        However at the point of instantiating a UDP, one can possibly control
the relative timing of the transitions by introducing appropriate delays on the
input lines.

That also allows modelling of set up and hold times.

Otherwise, the logical consequence of one transition must be considered prior
to deciding what the other transition will do. That will mean, perhaps a bigger
table.

Can someone please comment!



Thu, 02 Jan 1997 06:57:06 GMT  
 Prioritizing transitions in UDPs

Quote:

>Subject: Prioritizing transitions in UDPs
>I would like to know if there is a simple mechanism for prioritizing
>transitions when two or more inputs change simultaneously.

>(The UDP definition does not allow for multiple edges in the same
>UDP line. But real world inputs or simulation inputs occur in undefined
>unpredictable order)

>If prioritization is not done, this leads to race conditions and/or
>unpredictable results depending on the implementation of the simulator.

As Sitaram has noted, although he hasn't reached the conclusion,
1) Verilog is a hardware description language.
2) If your goal is to describe hardware, such that that hardware can
   actually be built, you must insure there are no "race conditions"
3) If your circuit goes to zero on a posedge of a, and goes to 1 on a
   posedge of b, you must insure that either
        a) posedge transitions on a and b do not occur within setup
           requirements of each other.
        b) other external logic prioritizes transitions on a and b.

This sounds so onerous; but consider what you are trying to do:
specify the behavior of hardware.  You are violating the design rules
by having two inputs change simultaneously.  Real hardware isn't so
discrete. Sometimes a will change ever so slightly ahead of b; other
times b will change first.

You must either arrange so that that doesn't happen, or design around
the simultaneity.
--


`------' A VIEWlogic Company      For information, call 1-800-VERILOG



Fri, 03 Jan 1997 02:54:30 GMT  
 Prioritizing transitions in UDPs
|> Hi there,
|> I would like to know if there is a simple mechanism for prioritizing
|> transitions when two or more inputs change simultaneously.
|>
|> (The UDP definition does not allow for multiple edges in the same
|> UDP line. But real world inputs or simulation inputs occur in undefined
|> unpredictable order)
|>
|> If prioritization is not done, this leads to race conditions and/or
|> unpredictable results depending on the implementation of the simulator.
|>

What are you looking to prioritize? There are a number of ways you can
write your model so that evaluations and updates occur independently
(unit delay gate models or no-blocking assignments)  

If you are trying to describe something like "set-overrides-reset",
you can check the level of set on the edge of reset.

--
___________________________________________________________

Cadence Design, 270 Billerica Rd., Chelmsford MA 01824-4140
"I used to have Time. Now I have Twins"
___________________________________________________________



Sat, 11 Jan 1997 02:55:40 GMT  
 
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