JOB FOR ENTRY-LEVEL ASIC DESIGN ENGINEER 
Author Message
 JOB FOR ENTRY-LEVEL ASIC DESIGN ENGINEER

Honeywell, Inc. Central Technical Operations, Phoenix Arizona, has a job
opening for a BS/MS EE/CS with 1-3 yrs experience designing or modeling
digital ASICs/FPGAs using VHDL and or Verilog.  Requires experience with
UNIX and one or more of the following tools:

  VHDL Simulator (e.g. Vantage, QuickHDL, MTI)
  Verilog Simulator (Verilog-XL, VCS)
  Synthesis (Synopsys)
  Test Synthesis (Test Compiler)
  Static Timing (Motive)
  Gate-Level Simulation (QuickSim)

Candidate must demonstrate ability to learn and apply new tools and
languages in a fast-paced, dynamic environment.  Must have good
communication skills and ability to work productively in a team
environment.

If you are interested please e-mail your resume to Kevin Locker,



Sat, 03 Jul 1999 03:00:00 GMT  
 
 [ 1 post ] 

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