VHDL to Verilog RTL translator available under GPL 
Author Message
 VHDL to Verilog RTL translator available under GPL

Hi,

We design cores which must be available both in VHDL and Verilog.
So, I wrote a translator that supports a limited but useful subset of
synthesisable
VHDL.

Although limited, this program correctly translated our Triple DES and
JPEG cores.
Since we have no commercial interest in such sw I decided to release it
in
the public domain under GPL.

The program is not particularly well written (my first attempt to use
YACC),
but it does a decent job at translating RTL, better, in some cases, than

some commercial programs I've seen.
This was a warm up exercise for a VHDL and Verilog to C, cycle based
compiler I have in mind. One day, maybe......

It is based on YACC/ C and it has been tested on Linux and Sun.
I believe that porting to Win should be easy.

You can fetch it at our download page:

http://www.*-*-*.com/

Regards,

Vincenzo Liguori
---------------------------------------------------------------------------

Vincenzo Liguori
Ocean Logic Pty Ltd
PO BOX 768
Manly NSW 1655
Australia

Ph : +61-2-99054152
Fax : +61-2-99050921
WWW : http://www.*-*-*.com/



Mon, 18 Aug 2003 06:03:37 GMT  
 
 [ 1 post ] 

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