REPOST: VHDL Testbenches For "The Great ESDA Shootout" 
Author Message
 REPOST: VHDL Testbenches For "The Great ESDA Shootout"


     /o o\  /  it's a FEATURE!"                              (508) 429-4357
    (  >  )
     \ - /         VHDL Testbenches for The Great ESDA Shootout
     _] [_          
                               by John Cooley

        Holliston Poor Farm, P.O. Box 6222, Holliston, MA  01746-6222

    Here's a copy of the two testbenches plus vector files for those who want
  to try for themselves the Great ESDA Shootout from the recent HP Design
  SuperCon.  To get the details of the contest, read the current issue of
  "Integrated System Design" magazine (it's in the April '96 issue which was
  mailed out to readers last week.)

    To run the first testbench using Cadence Leapfrog:

        UNIX>cv -m machine3.vhd tester3.vhd
        UNIX>ev -m work.tester:foo
        UNIX>sv -b -run work.tester:foo

    To run the Post-ECO testbench:

        UNIX>cv -m machine4.vhd tester4.vhd
        UNIX>ev -m work.tester:foo
        UNIX>sv -b -run work.tester:foo

    For those who try this contest at home: I'd like to hear how you do!
  For those who don't try but want to comment on the Shootout after reading
  about it, I'd like to hear what you have to say, too!

                                               - John Cooley
                                                 the ESNUG guy

-----------  template.vhd  -------------------------------------------------

library ieee, std;
use std.textio.all;
use ieee.std_logic_1164.all;

entity machine is
        port ( a, b : in std_logic;
                  c : in std_logic_vector(0 to 2);
              state : buffer std_logic_vector(0 to 3);
              clock : in std_logic;
              reset : in std_logic;
               d, e : in std_logic;
             dstate : buffer std_logic_vector(0 to 1);
             estate : buffer std_logic_vector(0 to 1);
               f, g : in std_logic;
               h, i : out std_logic);
end machine;

architecture gooby of machine is

begin

-- Put your design in here and relabel it "machine3.vhd"  !!!!!

end gooby;

-----------  tester3.vhd  --------------------------------------------------

--
--  "tester3.vhd" -- the VHDL testbench for use at the HP Design Supercon's
--   Great ESDA Shootout for testing "machine3.vhd" using "vector_file3.vec"
--

library ieee, std;
use std.textio.all;
use ieee.std_logic_1164.all;
-- use work.all;

entity tester is
end tester;

architecture foo of tester is

        function stdvc_2_str (inp : std_logic_vector ) return string is
                variable temp : string(1 to inp'right+1);
        begin
          for i in inp'range loop
                if (inp(i) = '1' ) then
                    temp(i+1) := '1';
                elsif (inp(i) = '0' ) then
                    temp(i+1) := '0';
                else
                    temp(i+1) := 'X';
                end if;
           end loop;
        return temp;
        end;

        function str_2_stdvc (inp : string ) return std_logic_vector is
                variable temp : std_logic_vector(0 to inp'right-1);
        begin
          for i in inp'range loop
                if (inp(i) = '1' ) then
                    temp(i-1) := '1';
                elsif (inp(i) = '0' ) then
                    temp(i-1) := '0';
                else
                    temp(i-1) := 'X';
                end if;
           end loop;
        return temp;
        end;

        function std_2_str (inp : std_logic ) return string is
                variable temp : string(1 to 1);
        begin
                if (inp = '1' ) then
                    temp(1) := '1';
                elsif (inp = '0' ) then
                    temp(1) := '0';
                else
                    temp(1) := 'X';
                end if;
        return temp;
        end;

        component machine
          port ( a, b : in std_logic;
                    c : in std_logic_vector(0 to 2);
                state : buffer std_logic_vector(0 to 3);
                clock : in std_logic;
                reset : in std_logic;
                 d, e : in std_logic;
               dstate : buffer std_logic_vector(0 to 1);
               estate : buffer std_logic_vector(0 to 1);
                 f, g : in std_logic;
             h, i : out std_logic);
        end component;

        for all : machine use entity work.machine(gooby);

        signal   a, b : std_logic := 'X';
        signal      c : std_logic_vector(0 to 2) := "XXX";
        signal  state : std_logic_vector(0 to 3) := "XXXX";
        signal  clock : std_logic := 'X';
        signal  reset : std_logic := 'X';
        signal   d, e : std_logic := 'X';
        signal dstate : std_logic_vector(0 to 1) := "XX";
        signal estate : std_logic_vector(0 to 1) := "XX";
        signal   f, g : std_logic := 'X';
        signal   h, i : std_logic := 'X';

        signal   done : std_logic := '0';

begin

process

        file test_vectors : text is in "vector_file3.vec";
        variable t_vec_line : line;
        variable t_vec_str : string(1 to 20);
        variable t_vec : std_logic_vector(0 to 19);
        variable george_out : std_logic_vector(0 to 9);
        variable george_expected : std_logic_vector(0 to 9);
        variable tmp_state : std_logic_vector(0 to 3);
        variable tmp_dstate : std_logic_vector(0 to 1);
        variable tmp_estate : std_logic_vector(0 to 1);
        variable tmp_h, tmp_i : std_logic;

        variable fileline : line;

begin

  reset <= '0';  
  wait until clock = '0' and clock'event;

  while (not endfile(test_vectors)) loop

        readline (test_vectors, t_vec_line);
        read (t_vec_line, t_vec_str);
        t_vec := str_2_stdvc(t_vec_str);

        a <= t_vec(0);
        b <= t_vec(1);
        c <= t_vec(2 to 4);
        d <= t_vec(10);
        e <= t_vec(11);
        f <= t_vec(16);
        g <= t_vec(17);
        tmp_state := t_vec(5 to 8);
        tmp_dstate := t_vec(12 to 13);
        tmp_estate := t_vec(14 to 15);
        tmp_h := t_vec(18);
        tmp_i := t_vec(19);

        reset <= t_vec(9);

        wait until clock = '0' and clock'event;

        george_out := ( state & dstate & estate & h & i);
        george_expected := ( t_vec(5 to 8) & t_vec(12 to 15) & t_vec(18 to 19));

        if ( george_expected = george_out ) then
          assert false
          report
          " INPUTS BEFORE positive edge of CLOCK                             reset = " &
          std_2_str(reset) & lf &
          "    were:  a = " & std_2_str(a) & "  b = " & std_2_str(b) & "  c = " &
          stdvc_2_str(c) & lf &
          "           d = " & std_2_str(d) & "  e = " & std_2_str(e) &
          "  f = " & std_2_str(f) & "  g = " & std_2_str(g) & lf &
          " AFTER positive edge of CLOCK:  state = " & stdvc_2_str(state) &
          "  dstate = " & stdvc_2_str(dstate) & "  estate = " &
          stdvc_2_str(estate) & "  h = " & std_2_str(h) & "  i = " & std_2_str(i) & lf &

          " Cool!  Just what I expected!         " & lf
          severity note;
        else
          assert false
          report
          "************** BAD NEWS, DUDE! *************" & lf &
          " INPUTS BEFORE positive edge  of CLOCK                            reset = " &
          std_2_str(reset) & lf &
          "    were:  a = " & std_2_str(a) & "  b = " & std_2_str(b) &
          "  c = " &
          stdvc_2_str(c) & lf &
          "           d = " & std_2_str(d) & "  e = " & std_2_str(e) &
          "  f = " & std_2_str(f) & "  g = " & std_2_str(g) & lf &

          " AFTER positive edge of CLOCK:  state = " & stdvc_2_str(state) &
          "  dstate = " & stdvc_2_str(dstate) & "  estate = " &
          stdvc_2_str(estate) & "  h = " & std_2_str(h) & "  i = " &
          std_2_str(i) & lf &

          "                   I EXPECTED:  state = " &
          stdvc_2_str(tmp_state) &
          "  dstate = " & stdvc_2_str(tmp_dstate) &
          "  estate = " & stdvc_2_str(tmp_estate) &
          "  h = " & std_2_str(tmp_h) &
          "  i = " & std_2_str(tmp_i) & lf &

          " ... check your state flow, dude.        " & lf
          severity failure;
          done <= '1';
        end if;

    end loop;

    assert false
    report lf & lf &
    "   ######   CONGRATS! -- THIS IS A FUNCTIONALLY CORRECT DESIGN!!!!   ###### "
    & lf & lf
    severity failure;
    done <= '1';

end process;

process      -- clock generation

begin

  while ( done = '0' ) loop
    clock <= '1';
    wait for 50 ns;
    clock <= '0';
    wait for 50 ns;
  end loop;

end process; -- clock generation

george : machine
    port map ( a, b, c , state, clock, reset, d, e, dstate, estate, f, g, h, i);

end foo;

-----------  vector_file3.vec  ---------------------------------------------

X0XXX00001XX00000000
X0111010100100001001
XX000010100100001100
XX010010101001011001
XX01101100XX01010000
XXXXX10000XX01010000
XXXXX00001XX00000000
X1XXX000100100000000
X0XXX001101001010110
XX10101000XX01011000
01XXX00100XX01010000
XX11100100XX01011100
XX00000010XX01010110
XXXXX00110XX01010000
XX01101010XX01011001
XXXXX00001XX00000100
X1XXX000101001010000
XXXXX00110XX01010000
XX10101000XX01010000
11XXX10000XX01010000
X0XXX11010XX10010000
XX000110100X11010000
XX01111100XX00010000
XXXXX111100X00010000
XXXXX000001X01010000
X0XXX01010XX01100000
XX01101100X101110000
XXXXX10000XX01000000
X1XXX10010X010010000
XXXXX101101X00010000
XX101110000X00010000
00XXX110001X01010000
01XXX10100XX01011001
XX10010100XX01010110
XX00010010XX01010000
XXXXX10110XX01010000
XX10111000XX01010000
1XXXX11110XX01010000
XXXXX00000XX01010000
X0XXX01010XX01100000
XX01101100X001000000
XXXXX10000X101000000
X1XXX100100010010000
XXXXX101101X00010000
XX011110101X01010000
XXXXX00001XX00000000
XXXXX00001XX00000000
XXXXX00001XX00000000
XXXXX00001XX00000000
XXXXX00001XX00000000
XXXXX00001XX00000000

-----------  tester4.vhd  --------------------------------------------------

--
--    "tester4.vhd" -- the VHDL testbench for use at the HP Design
--       Supercon's Great ESDA Shootout for testing the *post-ECO*
--       "machine4.vhd" using "vector_file4.vec"
--

library ieee, std;
use std.textio.all;
use ieee.std_logic_1164.all;
-- use work.all;

entity tester is
end tester;

architecture foo of tester is

        function stdvc_2_str (inp : std_logic_vector ) return string is
                variable temp : string(1 to inp'right+1);
        begin
          for i in inp'range loop
                if (inp(i) = '1' ) then
                    temp(i+1) := '1';
                elsif (inp(i) = '0' ) then
                    temp(i+1) := '0';
                else
                    temp(i+1) := 'X';
                end if;
           end loop;
        return temp;
        end;

        function str_2_stdvc (inp : string ) return std_logic_vector is
                variable temp : std_logic_vector(0 to inp'right-1);
        begin
          for i in inp'range loop
                if (inp(i) = '1' ) then
                    temp(i-1) := '1';
                elsif (inp(i) = '0' ) then
                    temp(i-1) := '0';
                else
                    temp(i-1) := 'X';
                end if;
           end loop;
        return temp;
        end;

        function std_2_str (inp : std_logic ) return string is
                variable temp : string(1 to 1);
        begin
                if (inp = '1' ) then
                    temp(1) := '1';
                elsif (inp = '0' ) then
                    temp(1) := '0';
                else
                    temp(1) := 'X';
                end if;
        return temp;
        end;

        component machine
          port ( a, b : in std_logic;
                    c : in std_logic_vector(0 to 2);
                state : buffer std_logic_vector(0 to 3);
                clock : in std_logic;
                reset : in std_logic;
                 d, e : in std_logic;
               dstate : buffer std_logic_vector(0 to 1);
               estate : buffer std_logic_vector(0 to 1);
                 f, g : in std_logic;
                 h, i : out std_logic);
        end component;

        for all : machine use entity work.machine(gooby);

        signal   a, b : std_logic := 'X';
        signal      c : std_logic_vector(0 to 2) := "XXX";
        signal  state : std_logic_vector(0 to 3) := "XXXX";
        signal  clock : std_logic := 'X';
        signal  reset : std_logic := 'X';
        signal   d, e : std_logic := 'X';
        signal dstate : std_logic_vector(0 to 1) := "XX";
        signal estate : std_logic_vector(0 to 1) := "XX";
        signal   f, g : std_logic := 'X';
        signal   h, i : std_logic := 'X';

        signal   done : std_logic := '0';

begin

process

        file test_vectors : text is in "vector_file4.vec";
        variable t_vec_line : line;
        variable t_vec_str : string(1 to 20);
        variable t_vec : std_logic_vector(0 to 19);
        variable george_out : std_logic_vector(0 to 9);
        variable george_expected : std_logic_vector(0 to 9);
        variable tmp_state : std_logic_vector(0 to 3);
        variable tmp_dstate : std_logic_vector(0 to 1);
        variable tmp_estate : std_logic_vector(0 to 1);
        variable tmp_h, tmp_i : std_logic;

        variable fileline : line;

begin

  reset <= '0';  
  wait until clock = '0' and clock'event;

  while (not endfile(test_vectors)) loop

        readline (test_vectors, t_vec_line);
        read (t_vec_line, t_vec_str);
        t_vec := str_2_stdvc(t_vec_str);

        a <= t_vec(0);
        b <= t_vec(1);
        c <= t_vec(2 to 4);
        d <= t_vec(10);
        e <= t_vec(11);
        f <= t_vec(16);
        g <= t_vec(17);
        tmp_state := t_vec(5 to 8);
        tmp_dstate := t_vec(12 to 13);
        tmp_estate := t_vec(14 to 15);
        tmp_h := t_vec(18);
        tmp_i := t_vec(19);

        reset <= t_vec(9);

        wait until clock = '0' and clock'event;

        george_out := ( state & dstate & estate & h & i);
        george_expected := ( t_vec(5 to 8) & t_vec(12 to 15) & t_vec(18 to 19));

        if ( george_expected = george_out ) then
          assert false
          report
          " INPUTS BEFORE positive edge of CLOCK                             reset = " &
          std_2_str(reset) & lf &
          "    were:  a = " & std_2_str(a) & "  b = " & std_2_str(b) & "  c = " &
          stdvc_2_str(c) & lf &
          "           d = " & std_2_str(d) & "  e = " & std_2_str(e) &
          "  f = " & std_2_str(f) & "  g = " & std_2_str(g) & lf &
          " AFTER positive edge of CLOCK:  state = " & stdvc_2_str(state) &
          "  dstate = " & stdvc_2_str(dstate) & "  estate = " &
          stdvc_2_str(estate) & "  h = " & std_2_str(h) & "  i = " & std_2_str(i) & lf &

          " Cool!  Just what I expected!         " & lf
          severity note;
        else
          assert false
          report
          "************** BAD NEWS, DUDE! *************" & lf &
          " INPUTS BEFORE positive edge  of CLOCK                            reset = " &
          std_2_str(reset) & lf &
          "    were:  a = " & std_2_str(a) & "  b = " & std_2_str(b) &
          "  c = " &
          stdvc_2_str(c) & lf &
          "           d = " & std_2_str(d) & "  e = " & std_2_str(e) &
          "  f = " & std_2_str(f) & "  g = " & std_2_str(g) & lf &

          " AFTER positive edge of CLOCK:  state = " & stdvc_2_str(state) &
          "  dstate = " & stdvc_2_str(dstate) & "  estate = " &
          stdvc_2_str(estate) & "  h = " & std_2_str(h) & "  i = " &
          std_2_str(i) & lf &

          "                   I EXPECTED:  state = " &
          stdvc_2_str(tmp_state) &
          "  dstate = " & stdvc_2_str(tmp_dstate) &
          "  estate = " & stdvc_2_str(tmp_estate) &
          "  h = " & std_2_str(tmp_h) &
          "  i = " & std_2_str(tmp_i) & lf &

          " ... check your state flow, dude.        " & lf
          severity failure;
          done <= '1';
        end if;

    end loop;

    assert false
    report lf & lf &
    "   ######   CONGRATS! -- THIS IS A *Post-ECO* CORRECT DESIGN!!!!   ###### "
    & lf & lf
    severity failure;
    done <= '1';

end process;

process      -- clock generation

begin

  while ( done = '0' ) loop
    clock <= '1';
    wait for 50 ns;
    clock <= '0';
    wait for 50 ns;
  end loop;

end process; -- clock generation

george : machine
    port map ( a, b, c , state, clock, reset, d, e, dstate, estate, f, g, h, i);

end foo;

-----------  vector_file4.vec  ---------------------------------------------

XXXXX00101XX00110000
X0XXX00000XX01000000
X1XXX00010X101000000
XXXXX00010X101001100
XXXXX00110X001010110
XX10101000XX01011000
1XXXX10000XX01010110
X1XXX10010XX11011100
XXXXX100100X00010000
X1XXX101101X10011100
X1101110001X10011000
01XXX101001X10011001
XX101101000X11010000
XX00010010XX00011000
X0XXX100100X01011000
XXXXX101101X01011000
XX01111100XX01011000
XXXXX11110XX01011000
XXXXX00100XX01011000
XXXXX00000XX01100100
X1XXX00010X001000100
XXXXX00110X001011000
XX10101000XX01011000
0111001000XX01011000
0000001000XX01011000
0101001000XX01011000
0100000010XX01011000
XXXXX00110X001011000
XX10001110XX01011000
XXXXX01010XX01011001
XX11001010XX01010000
XX01101100XX01011000
XXXXX10000XX01011000
X0XXX11010XX11011000
XX10011010XX00011000
X001111100XX01011000
XXXXX11110XX01011000
XXXXX00100XX01011000
XXXXX00000XX01101000
X0XXX01010X101111001
XXXXX00101XX00111000
XXXXX00101XX00111000
XXXXX00101XX00111000
XXXXX00101XX00111000
XXXXX00101XX00111000

===========================================================================
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     /o o\  /  it's a FEATURE!"                 (508) 429-4357
    (  >  )
     \ - /     - John Cooley, EDA & ASIC Design Consultant in Synopsys,
     _] [_         Verilog, VHDL and numerous Design Methodologies.

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Mon, 02 Nov 1998 03:00:00 GMT  
 
 [ 1 post ] 

 Relevant Pages 

1. REPOST: VHDL Testbenches For "The Great ESDA Shootout"

2. (VHDL) Testbenches For The Great ESDA Shootout

3. (VHDL) Testbenches For The Great ESDA Shootout

4. (Verilog) Testbenches For The Great ESDA Shootout

5. (Verilog) Testbenches For The Great ESDA Shootout

6. REPOST: Verilog Testbenches For "The Great ESDA Shootout"

7. REPOST: Verilog Testbenches For "The Great ESDA Shootout"

8. *** The Great ESDA Shootout ***

9. ** ASIC Designers Wanted For Next Week's Great ESDA Shootout **

10. *** The Great ESDA Shootout ***

11. Paper online: "Web Framework Shootout"

12. creating/using "subroutines" in Verilog testbenches

 

 
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