Xilinx Foundation Series 1.5 Verilog RAMs 
Author Message
 Xilinx Foundation Series 1.5 Verilog RAMs

This is a rather specific question, so I apologize if this is out of
place.
I am using Xilinc's Foundation Series 1.5 to prototype a Verilog HDL
design
on a Xilinx 4010XL part.  Is there a way to instantiate a Xilinx
macroblock
(in this case, one of the RAM blocks) inside the Verilog HDL code?

Or am I better off leaving inputs and outputs at the Verilog module
boundary,
then connecting the RAM and my verilog 'macro' inside the schematic
capture
tool?  I would like to keep everything in veriloga s much as possible,
for
better portability.  (Though obviously, instantiating a specific Xilinx
FPGA library macrocell inside the RTL code runs counter to this goal.)



Mon, 06 Jan 2003 03:00:00 GMT  
 
 [ 1 post ] 

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