Xilinx Foundation Series 1.5 Verilog RAMs 
Author Message
 Xilinx Foundation Series 1.5 Verilog RAMs

This is a rather specific question, so I apologize if this is out of
I am using Xilinc's Foundation Series 1.5 to prototype a Verilog HDL
on a Xilinx 4010XL part.  Is there a way to instantiate a Xilinx
(in this case, one of the RAM blocks) inside the Verilog HDL code?

Or am I better off leaving inputs and outputs at the Verilog module
then connecting the RAM and my verilog 'macro' inside the schematic
tool?  I would like to keep everything in veriloga s much as possible,
better portability.  (Though obviously, instantiating a specific Xilinx
FPGA library macrocell inside the RTL code runs counter to this goal.)

Mon, 06 Jan 2003 03:00:00 GMT  
 [ 1 post ] 

 Relevant Pages 

1. xilinx foundation series/ xilinx student edition software

2. Xilinx foundation series software

3. Xilinx Foundation Sudent Edition and The Practical Xilinx Designer Lab Book

4. Future directions of Fortran # 1.5 in a series

5. Xilinx student edition, version 1.5

6. Should I bother with Xilinx Foundation 1.5 vs 2.1?

7. Should I bother with Xilinx Foundation 1.5 vs 2.1?

8. Xilinx Foundation 2.1i

9. Xilinx Foundation Software Eval Pkg Won't Instal

10. XILINX Foundation UCF Problem


12. Xilinx Foundation F2.1i SE


Powered by phpBB® Forum Software