Think like a hardware designer.
In real hardware there are only flops and gates.
If you can master how to write hdl for them and get desired results after
synthesis you have achieved 80% mastery.
You are not declaring SDA flop in reset.
Here is correct pseudo code
begin
if (reset)
begin
SLAVEID <= 6'b101000;
SDA <= 1'b0;
end
else
begin
if ((timer >= 7) && (timer < 11)) SDA <= SLAVEID[5];
else if ......................
end
end
Hope this helps
Rajesh Ba{*filter*}ule
Verilog FAQ http://www.*-*-*.com/
Quote:
> Say I want to set the value of a register upon reset, and then set another
> register to to the individual bits of that register at different points in
> time, as follows:
> _____________________________________
> begin
> if (reset) SLAVEID <= 6'b101000;
> if (~(reset)) begin
> if ((timer >= 7) && (timer < 11)) SDA <= SLAVEID[5]; file://1;
> else if ((timer >= 11) && (timer < 15)) SDA <= SLAVEID[4]; file://0;
> else if ((timer >= 15) && (timer < 19)) SDA <= SLAVEID[3]; file://1;
> else if ((timer >= 19) && (timer < 23)) SDA <= SLAVEID[2]; file://0;
> else if ((timer >= 23) && (timer < 27)) SDA <= SLAVEID[1]; file://0;
> else if ((timer >= 27) && (timer < 31)) SDA <= SLAVEID[0]; file://0;
> end file://end if
> end // end always
> _________________________________________
> For some reason, this does not work (the SDA register does not take on the
> appropriate values after the reset). Can someone tell me what I'm doing
> wrong here? Thanks!
> Vik
Reset Question