Incorrect example in P1364 p9-4 
Author Message
 Incorrect example in P1364 p9-4

Does anyone know what the (incorrect?) example on p.9-4, section 9.2.2
of the October draft P1364 is trying to say?

it claims that


 a<=b;
 b<=a;
end

is executed in two steps;

1 the right hand sides of the assignments are evaluated and assignments
scheduled at posedge c.
2 at posedge c the lefthand sides are updated,

This is a joke? Surely the begin...end block is suspended until posedge
c, at which time the rhs's are evaluated and scheduled as "non-blocking
assign update events" (section 5) - ie to happen at the end of this
time-step (notwithstanding any other blocked statements which are
unblocked by the changes to a and b...)

--
Daryl Stewart
RA to EPSRC Verilog Formal Equivalence Project
http://www.*-*-*.com/ :80/users/djs1002/verilog.project/



Sat, 31 Oct 1998 03:00:00 GMT  
 Incorrect example in P1364 p9-4

It is trying to say that this executes a swap of the registers a and b.


 a<=b;
 b<=a;
end

At the event positive edge c, tmpb = b and tmpa = a are performed. Then
after a time step (of ZERO!) the left-hand assignements are made as
a = tmpb, b = tmpa.

If the code had been:


 a=b;
 b=a;
end


and the value of a would be lost

--
Gerard M Blair, Senior Lecturer, The Department of Electrical Engineering,
              The University of Edinburgh, Scotland, UK



Sat, 31 Oct 1998 03:00:00 GMT  
 Incorrect example in P1364 p9-4

Quote:

> Does anyone know what the (incorrect?) example on p.9-4, section 9.2.2
> of the October draft P1364 is trying to say?

> it claims that


>  a<=b;
>  b<=a;
> end

> is executed in two steps;

> 1 the right hand sides of the assignments are evaluated and assignments
> scheduled at posedge c.
> 2 at posedge c the lefthand sides are updated,

> This is a joke? Surely the begin...end block is suspended until posedge
> c, at which time the rhs's are evaluated and scheduled as "non-blocking
> assign update events" (section 5) - ie to happen at the end of this
> time-step (notwithstanding any other blocked statements which are
> unblocked by the changes to a and b...)

This is not a joke, it is called "bug".  The explanation in this
section only help to confuse matter.  It should be fixed by the
draft committee.

Quote:

> --
> Daryl Stewart
> RA to EPSRC Verilog Formal Equivalence Project
> http://www.cl.cam.ac.uk:80/users/djs1002/verilog.project/

tan
consultant
silicon-sorcery




Sun, 01 Nov 1998 03:00:00 GMT  
 
 [ 3 post ] 

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