Non blocking assign question 
Author Message
 Non blocking assign question

I ran in to the following type of circuit involving non blocking assigns
in the OVI test suite. I am posting this because I'm am not sure how it is
supposed to work.

module top;
 reg a, clk;

 initial a = 0;
 initial clk = 100;
 always #100 clk = ~clk;
 always
  begin : foo

  end
 initial  
  $monitor($stime,, "clk=%b a=%b", clk, a);  
endmodule

It seems to me the assignment at time 15, 115, 215, etc. should never happen
because the named block foo terminates thereby canceling any pending
non blocking assignment events.  But OVI sim executes the assignments.
Can anyone help me understand the semantics?
/Steve
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Steve Meyer                             Phone: (415) 296-7017
Pragmatic C Software Corp.              Fax:   (415) 781-1116

San Francisco, CA 94104



Sun, 20 Apr 1997 03:39:23 GMT  
 Non blocking assign question

Quote:

>I ran in to the following type of circuit involving non blocking assigns
>in the OVI test suite. I am posting this because I'm am not sure how it is
>supposed to work.
>module top;
> reg a, clk;
> initial a = 0;
> initial clk = 100;
> always #100 clk = ~clk;
> always
>  begin : foo

>  end
> initial  
>  $monitor($stime,, "clk=%b a=%b", clk, a);  
>endmodule
>It seems to me the assignment at time 15, 115, 215, etc. should never happen
>because the named block foo terminates thereby canceling any pending
>non blocking assignment events.  But OVI sim executes the assignments.
>Can anyone help me understand the semantics?

There are only three things that can prevent a non-blocking assignment
from occuring after the assignment statement is executed.

1. the event control never get triggered, because sim time was not advanced

2. a procedural continious assigment is in effect (assign a = 0;)

3. The named block containing the assignment is disabled (disable foo;)

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___________________________________________________________

Nextwave Design, 30 Cardinal Ln., Litchfield, NH 03051-2505
"I used to have Time. Now I have Twins"
___________________________________________________________



Sun, 20 Apr 1997 11:51:44 GMT  
 Non blocking assign question

Quote:
>I ran in to the following type of circuit involving non blocking assigns
>in the OVI test suite. I am posting this because I'm am not sure how it is
>supposed to work.
>module top;
> reg a, clk;
> initial a = 0;
> initial clk = 100;
> always #100 clk = ~clk;
> always
>  begin : foo

>  end
> initial  
>  $monitor($stime,, "clk=%b a=%b", clk, a);  
>endmodule
>It seems to me the assignment at time 15, 115, 215, etc. should never happen
>because the named block foo terminates thereby canceling any pending
>non blocking assignment events.  But OVI sim executes the assignments.
>Can anyone help me understand the semantics?

I do not know what this example is supposed to illustrate -- at least in
any real world type of circuit.  But, the always procedures will run
concurrently, and both will execute their assignment statements until
you get tired of wathcing the output and abort the simulation.  I note
the following:

1. The "initial clk = 100;" statement will set the variable "clk" to
   a value of 1-bit zero, since "clk" is scalar.

2. The named block "foo", is not required, since nothing uses the name
   or hierarchy scope created by the name (typically, a named block is
   used so that their can either be local variables declared within the
   block, or so that events shceduled within the block can be canceled
   using the "disable" statement).


   assignment, because there are no other events that will ever be
   scheduled at the same time.  The purpose of the non-blocking assignment
   is to give the modeler some control over what order events will be
   evaluated and assigned, when several events may occur at the same
   moment in simulation time.  The statement in question will do the
   following, in order:

   1). Wait for any change on clk (which will be at times: 100, 200,
       300, ...).

   2). Wait 10 more time units (specified by the "#10").

   3). EVALUATE the expression "~a" (binary inversion of "a");  Note that
       this is only the evaluation of the expression -- the result of
       the evaluation is not yet assigned.

   4). Wait 5 more time units (specified by the intra-assignment delay of
       "#5"); this brings simulation time up to clock change + 15.

   5). Wait until all blocking assignements and expression evaluations
       at the current time unit (clock change + 15) have been executed
       (specified by the non-blocking assignment "<="), then assign "a" the
       previously evaluated result of "~a".  Note that if "a" had changed
       any time between clock + 10 and clock + 15 (including during
       clock + 15), the old value of "~a" would still be used, since it
       was evaluated at clock + 10.

   6). Repeat the loop forever (specified by the "always" procedure).

4. Finally, even if there were multiple assignments occurring at the same
   time, which the non-blocking assignment caused to be assigned in a
   specific order, this test would never show it, because the "$monitor"
   statement is specifically defined to only print messages once in a
   given time step, after all events in the time step have completed.

So, as I said, I haven't got a clue as to what this example is supposed to
test, unless perhaps, it is intened to test a parser.  It has no functional
purpose.

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Sun, 20 Apr 1997 23:48:49 GMT  
 Non blocking assign question
In reply to the various replies to my original question on non blocking
assigns:

  1) There is a bug in the circuit I posted, the declaration for clock
     is only 1 bit, it should be "reg [31:0] clock;" or something.

  2) The circuit is from the OVI test suite (10/10.1/d940412_130008)
     contributed by System Sciences.  I removed the disable testing
     part of the test.

  3) The circuit is a meaningless test circuit that abstracts something
     that I believe is a real question and does come up in larger designs.

     As one of the replies pointed out, according to the LRM, "evaluated
     and scheduled" non blocking assigns are only removed if a block is
     disabled.  Therefore, there is a functional difference depending on
     whether a block terminates by completing the last statement or being
     disabled.  It seems to me that disble and jump to block end should
     possibly have the same meaning since in both case control passes to
     the statement just after the block.  I am writing a simulator and the
     OVI sim interpretation means the control thread for terminated blocks
     must be kept around until all pending non blocking assigns have
     completed.  Is it then possible to disabled a block whose statements
     but not non blocking assignments has completed.  But I guess this
     is the rigth way to model the underlying hardware.

Thanks to all those who replied.
/Steve
--
Steve Meyer                             Phone: (415) 296-7017
Pragmatic C Software Corp.              Fax:   (415) 781-1116

San Francisco, CA 94104



Tue, 22 Apr 1997 03:46:56 GMT  
 
 [ 4 post ] 

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