Verilog vs VHDL 
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 Verilog vs VHDL

Can someone point out semantic differences between VHDL and verilog?

Possibly how is simulating designs is different for VHDL and verilog ?

Sharp.



Sat, 11 Jan 2003 03:00:00 GMT  
 Verilog vs VHDL
Can someone point out semantic differences between VHDL and verilog?

Possibly how is simulating designs is different for VHDL and verilog ?

John.



Sat, 11 Jan 2003 03:00:00 GMT  
 Verilog vs VHDL
: Can someone point out semantic differences between VHDL and verilog?

: Possibly how is simulating designs is different for VHDL and verilog ?

: Sharp.

Find a textbook that shows design examples in both VHDL and verilog.
The VHDL code will usually be 2-3X the size of the verilog code.

John Eaton



Sat, 11 Jan 2003 03:00:00 GMT  
 Verilog vs VHDL

Quote:


>: Can someone point out semantic differences between VHDL and verilog?
>: Possibly how is simulating designs is different for VHDL and verilog ?
>Find a textbook that shows design examples in both VHDL and verilog.
>The VHDL code will usually be 2-3X the size of the verilog code.

I can confirm that.  I rewrote a large chip from VHDL to Verilog, and
it then occupied one half the number of lines and one third the number
of characters.  The original VHDL already had abbreviations for the
really verbose terms like 'std_logic_vector', so the savings came from
the general terse-ness of Verilog.

My experience is that VHDL is so verbose that it impedes the understanding
the logic.  No amount of strong type-checking will improve the
reliability of incomprehensible logic.  Reliability comes more from
clarity than from syntax.  Plus you spend so much time writing the
overhead of VHDL that you have less time to think about it and debug
it.

--



Sun, 12 Jan 2003 03:00:00 GMT  
 Verilog vs VHDL

Quote:

>Possibly how is simulating designs is different for VHDL and verilog ?

In VHDL, you don't have direct access to any signal in the design.
You have to play games to get at it (all the solutions I've seen are
a pain in the you-know-what).  With Verilog you can get at anything
directly.

Test fixtures are a bit more bloated and many things (printf, etc.)
useful in test fixtures are not built into VHDL.  You have to write
extra code to do truly useful testbenches.  

I've even tried the mixed language approach (VHDL code, Verilog
testbench), but I ended up crashing Modelsim on a couple pieces and
abandoned it.  If you've got a VHDL/Verilog simulator, though, give
it a try.

VHDL does have some features that Verilog lacks, but I've found that
the aggravation, type conversion garbage, and extra typing of VHDL
more than tips the scales back the other way.

Superlog is looking to be attractive in the near future, though.

Dan



Tue, 14 Jan 2003 03:00:00 GMT  
 Verilog vs VHDL

Quote:


> Superlog is looking to be attractive in the near future, though.

> Dan

I spent some time chatting with sales drones at a trade show. I asked
about openness of the language, etc., with the idea that I would start
adding support in Icarus Verilog.

Basically, I was told that Superlog is proprietary and will remain
so until a market is developed to a point where it makes sense to
make it a public standard. Whatever that means.

At that point I put it out of my mind and moved on. As an EDA tool
vendor there was nothing I could do, and as a potential user (which
I am not, mind you) I couldn't imagine basing my future legacy on a
single-source, privately defined tool.

(Xilinx is bad enough, thank you:-)
--
Steve Williams                "The woods are lovely, dark and deep.


http://www.picturel.com       And lines to code before I sleep."



Tue, 14 Jan 2003 03:00:00 GMT  
 
 [ 6 post ] 

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