Force Evaluation 
Author Message
 Force Evaluation

Greetings:

        I have working on an interesting problem where
        I would use $readmemh to backdoor load a ram,
        but when I went to access the ram  the first
        location would always be x's. It turns out the
        Verilog wouldn't schedule an event to read the
        ram because it thought nothing was in there
        in the first place. Only when the address bits
        changed would it schedule an event to evaluate
        this module. My question is there a way to
        force Verilog to always re-evaluate a module?
        I have put in a work around where I do a force
        on the address lines and then release after #2,
        but I have a lot of rams to load in different
        modules and would prefer not to do this.

        Thanks for any help/insight in advance

        Tom



Tue, 30 Oct 2001 03:00:00 GMT  
 
 [ 1 post ] 

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