illegal left-hand-side assignment 
Author Message
 illegal left-hand-side assignment


Quote:
>   I have something like:
>output [7:0] x;

>reg [7:0] r0, r1, r2;

>if I say x = r0 I get the Illegal left-hand-side error.

>it I say assign x = r0, I still get the same error.

The assign statement should work.  This is pretty routine
in fact (although some designers prefer to double-declare
"x" by having it also be a wire, that is not required).

The following file produces no errors from Cadence:

    module mymodule(x);
    output [7:0] x;
    reg [7:0] r0;
    assign x = r0;
    endmodule

Probably you have some other syntax error somewhere, and
the error report is confused.

Steve



Wed, 05 Apr 2000 03:00:00 GMT  
 illegal left-hand-side assignment

Hi,
   I have something like:
output [7:0] x;

reg [7:0] r0, r1, r2;

if I say x = r0 I get the Illegal left-hand-side error.

it I say assign x = r0, I still get the same error.

What should I do?

Vangal.



Wed, 05 Apr 2000 03:00:00 GMT  
 illegal left-hand-side assignment

Quote:

> Hi,
>    I have something like:
> output [7:0] x;

> reg [7:0] r0, r1, r2;

> if I say x = r0 I get the Illegal left-hand-side error.

> it I say assign x = r0, I still get the same error.

> What should I do?

> Vangal.

        In order to say 'x = r0' in behavi{*filter*}code, you must define x
to be a register:

module foo(o,i, e);
   input  [7:0] i;
   input        e;
   output [7:0] o;
   reg [7:0] o; // this line says o is a register (and hence can hold
                // values, and be the target of behavi{*filter*}code)


        if(e) begin
           o = i; // o is the target
        end
   end

endmodule // foo

An alternative possible coding style:  

module foo(o,i, e);
   input  [7:0] i;
   input        e;
   output [7:0] o;

   assign o = e ? i : o;   // the declarative assign only targets wires; and by default outputs are wires.

endmodule // foo

module foo(o,i, e);
   input  [7:0] i;
   input        e;
   output [7:0] o;
   reg [7:0]    o; // this line says o is a register (and hence be the target of behavi{*filter*}assigns)


        if(e) begin
           assign o = i; // this may look like a declarative assign, but it isn't.
                         // Think of it as a weak 'force', which targets only registers
        end
   end

endmodule // foo

--
Michael McNamara     Silicon Sorcery  [37 15.7878' -121 57.4658']
Get my verilog emacs mode (subscribe for free updates!) at
             < http://www.*-*-*.com/ ;



Fri, 07 Apr 2000 03:00:00 GMT  
 illegal left-hand-side assignment

:i think you are using the assign statemnent in a sequential block.
:you can not do that for a wire. try using the assign assing as a concurrent


: >   I have something like:
: >output [7:0] x;
: >
: >reg [7:0] r0, r1, r2;
: >
: >if I say x = r0 I get the Illegal left-hand-side error.
: >
: >it I say assign x = r0, I still get the same error.

: The assign statement should work.  This is pretty routine
: in fact (although some designers prefer to double-declare
: "x" by having it also be a wire, that is not required).

: The following file produces no errors from Cadence:

:     module mymodule(x);
:     output [7:0] x;
:     reg [7:0] r0;
:     assign x = r0;
:     endmodule

: Probably you have some other syntax error somewhere, and
: the error report is confused.

: Steve



Sat, 08 Apr 2000 03:00:00 GMT  
 illegal left-hand-side assignment

This is a common error, and is explained in chapter 13 (common errors)
of the book "Verilog Quickstart".

Basically your problem, due to the error message and the declaration
that you show, is that x is a wire.  Wires must be driven continuously
by something like a gate.  If you think abou the real world you cant
just tell a wire to take a value and hold it, it needs to be driven
continuously as well if you expect it to hold a value.  You could use a
continuous assignment to drive the wire, or declare the output x to be a
reg then you could use a procedural assignment to update the value.

Please pick up a copy of "Verilog Quickstart" and read chapter 13,
"Common Errors".

-- James

Quote:

> Hi,
>    I have something like:
> output [7:0] x;

> reg [7:0] r0, r1, r2;

> if I say x = r0 I get the Illegal left-hand-side error.

> it I say assign x = r0, I still get the same error.

> What should I do?

> Vangal.

--
-.-. --.- -.-. --.- -.. . -. .---- -.. -.. -.- -..-. .-- -....

  Verilog Instructor      http://c118618-a.frmt1.sfba.home.com
  Author "Verilog Quickstart" ISBN 0-7923-9927-7
-.-. --.- -.-. --.- -.. . -. .---- -.. -.. -.- -..-. .-- -....


Sat, 08 Apr 2000 03:00:00 GMT  
 illegal left-hand-side assignment

Quote:

>This is a common error, and is explained in chapter 13 (common errors)
>of the book "Verilog Quickstart".
>You could use a
>continuous assignment to drive the wire, or declare the output x to be a
>reg then you could use a procedural assignment to update the value.
>> if I say x = r0 I get the Illegal left-hand-side error.

>> it I say assign x = r0, I still get the same error.

So isn't that a continious assignment?

Cheers Terry...



Mon, 10 Apr 2000 03:00:00 GMT  
 illegal left-hand-side assignment

Quote:


>>This is a common error [..]
>>You could use a
>>continuous assignment to drive the wire, or declare the output x to be a
>>reg then you could use a procedural assignment to update the value.
>>> if I say x = r0 I get the Illegal left-hand-side error.
>>> it I say assign x = r0, I still get the same error.
>So isn't that a continious assignment?

Yeah it is.  It would work, if it was outside of an always
statement.  Apparently the original poster's problem was he
had it inside an always statement.

Steve



Mon, 10 Apr 2000 03:00:00 GMT  
 illegal left-hand-side assignment

Quote:



> >>This is a common error [..]
> >>You could use a
> >>continuous assignment to drive the wire, or declare the output x to be a
> >>reg then you could use a procedural assignment to update the value.

> >>> if I say x = r0 I get the Illegal left-hand-side error.
> >>> it I say assign x = r0, I still get the same error.

> >So isn't that a continious assignment?

> Yeah it is.  It would work, if it was outside of an always
> statement.  Apparently the original poster's problem was he
> had it inside an always statement.

        And inside a behavi{*filter*}block (i.e. inside an always or
initial block) the `assign' keyword isn't a continuous assignement,
but rather a force of a register.

        Remember, nets and registers can appear on the right hand side
of any expression anywhere; but in behavi{*filter*}blocks, ONLY REGISTERS
can appear on the left hand side; and in structural code, ONLY NETS
can appear on the left hand side.

        The exception, of course, is the force statement, which is the
little red wire that one can use to drive anything to any value. Use caution!

--
Michael McNamara     Silicon Sorcery  [37 15.7878' -121 57.4658']
Get my verilog emacs mode (subscribe for free updates!) at
             < http://www.*-*-*.com/ ;



Mon, 10 Apr 2000 03:00:00 GMT  
 
 [ 8 post ] 

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